Add DRC ERC and LVS for calibre flows (4fb0045d) · Commits · SoCLabs / NanoSoC Tech · GitLab

Skip to content

GitLab

Explore

Sign in
Register

Primary navigation

Project

NanoSoC Tech
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Jira
- Terraform modules
- Incidents

Snippets Groups Projects

4fb0045d

Commit 4fb0045d authored 1 year ago by Daniel Newbrook

Downloads
- Patches
- Plain Diff

Add DRC ERC and LVS for calibre flows

parent 60a1204a

No related branches found

No related tags found

No related merge requests found

Changes 8

Hide whitespace changes

Inline Side-by-side

Showing

ASIC/44pin/Cadence/scripts/place_macros.tcl 6 additions, 4 deletions

ASIC/44pin/Cadence/scripts/place_macros.tcl
ASIC/44pin/Cadence/scripts/pnr_flow.tcl 19 additions, 3 deletions

ASIC/44pin/Cadence/scripts/pnr_flow.tcl
ASIC/44pin/Cadence/scripts/power_plan.tcl 2 additions, 2 deletions

ASIC/44pin/Cadence/scripts/power_plan.tcl
ASIC/44pin/Cadence/scripts/power_route.tcl 1 addition, 1 deletion

ASIC/44pin/Cadence/scripts/power_route.tcl
ASIC/44pin/Mentor/DRC 17 additions, 0 deletions

ASIC/44pin/Mentor/DRC
ASIC/44pin/Mentor/ERC 17 additions, 0 deletions

ASIC/44pin/Mentor/ERC
ASIC/44pin/Mentor/LVS 3 additions, 3 deletions

ASIC/44pin/Mentor/LVS
ASIC/constraints.sdc 1 addition, 1 deletion

ASIC/constraints.sdc

with 66 additions and 14 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment