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Commit 4fb0045d authored by Daniel Newbrook's avatar Daniel Newbrook
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Add DRC ERC and LVS for calibre flows

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ASIC/44pin/Cadence/scripts/place_macros.tcl
+ 6
− 4
View file @ 4fb0045d
...@@ -11,12 +11,14 @@ ...@@ -11,12 +11,14 @@
# relative floorplan # relative floorplan
gui_set_draw_view fplan gui_set_draw_view fplan
delete_relative_floorplan -all delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500} move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420} update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420}
add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4 add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
......
ASIC/44pin/Cadence/scripts/pnr_flow.tcl
+ 19
− 3
View file @ 4fb0045d
...@@ -68,16 +68,29 @@ source filler.tcl ...@@ -68,16 +68,29 @@ source filler.tcl
### Routing ### Routing
source route.tcl source route.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_early.rep
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_late.rep
check_antenna check_antenna
write_db nanosoc_chip_pads write_db nanosoc_chip_pads
delete_routes -net VDDIO delete_routes -net VDDIO
delete_routes -net VSSIO
source place_bondpads.tcl source place_bondpads.tcl
check_drc -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_drc.rep
check_filler -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_filler.rep
check_connectivity -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_connectivity.rep
check_process_antenna -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_antenna.rep
gui_show gui_show
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_default_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_default_late.mtarpt
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_typical_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_typical_late.mtarpt
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \ write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
-map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \ -map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
-lib_name DesignLib \ -lib_name DesignLib \
...@@ -87,9 +100,12 @@ write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \ ...@@ -87,9 +100,12 @@ write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_early.rep
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view] set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical.rep report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_early.rep
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view] set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
......
ASIC/44pin/Cadence/scripts/power_plan.tcl
+ 2
− 2
View file @ 4fb0045d
...@@ -57,7 +57,7 @@ set_db add_stripes_trim_antenna_back_to_shape none ...@@ -57,7 +57,7 @@ set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0 set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer AP set_db add_stripes_stacked_via_top_layer M9
set_db add_stripes_stacked_via_bottom_layer M4 set_db add_stripes_stacked_via_bottom_layer M4
set_db add_stripes_via_using_exact_crossover_size false set_db add_stripes_via_using_exact_crossover_size false
set_db add_stripes_split_vias false set_db add_stripes_split_vias false
...@@ -65,7 +65,7 @@ set_db add_stripes_orthogonal_only true ...@@ -65,7 +65,7 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring } set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell } set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape } set_db add_stripes_skip_via_on_wire_shape { noshape }
add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 2 -spacing 2 -set_to_set_distance 20 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit M9 -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit M9 -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all deselect_obj -all
......
ASIC/44pin/Cadence/scripts/power_route.tcl
+ 1
− 1
View file @ 4fb0045d
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
# Author : Srimanth Tenneti # Author : Srimanth Tenneti
################################## ##################################
route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) } route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
set_db route_special_via_connect_to_shape { padring stripe }
route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) } route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) } route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
......
ASIC/44pin/Mentor/DRC 0 → 100644
+ 17
− 0
View file @ 4fb0045d
*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/drc/calibre.drc
*drcRulesFileLastLoad: 1708424374
*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
*drcLayoutPrimary: nanosoc_chip_pads
*drcResultsFile: DRC_RES.db
*drcResultsCheckText: 1
*drcResultsCheckTextValue: ALL
*drcCellName: 0
*drcDRCMaxResultsAll: 1
*drcSummaryFile: DRC.rep
*drcActiveRecipe: Checks selected in the rules file
*drcUserRecipes: {{Checks selected in the rules file}}
*cmnResolution: 5
*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
ASIC/44pin/Mentor/ERC 0 → 100644
+ 17
− 0
View file @ 4fb0045d
*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/util/MAIN_DECK/CALIBRE_FLOW/nonUTM/DFM_LVS_RC_CAL_N65_ALRDL_noU_v16a.9m
*drcRulesFileLastLoad: 1708424374
*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc_fanis_20_02_24.gds
*drcLayoutPrimary: nanosoc_chip_pads
*drcResultsFile: DRC_RES.db
*drcResultsCheckText: 1
*drcResultsCheckTextValue: ALL
*drcCellName: 0
*drcDRCMaxResultsAll: 1
*drcSummaryFile: DRC.rep
*drcActiveRecipe: Checks selected in the rules file (Modified)
*drcUserRecipes: {{Checks selected in the rules file (Modified)} {{group_unselect[1]} all {group_select[1]} rule_file}}
*cmnResolution: 5
*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
ASIC/44pin/Mentor/LVS
+ 3
− 3
View file @ 4fb0045d
*lvsRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/lvs/calibre.lvs *lvsRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/lvs/calibre.lvs
*lvsRunDir: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/./LVS *lvsRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/LVS
*lvsLayoutPaths: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/nanosoc_srimanth_17_02_24.gds *lvsLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
*lvsLayoutPrimary: nanosoc_chip_pads *lvsLayoutPrimary: nanosoc_chip_pads
*lvsSourcePath: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v *lvsSourcePath: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v
*lvsSourceSystem: VERILOG *lvsSourceSystem: VERILOG
*lvsSourcePrimary: nanosoc_chip_pads *lvsSourcePrimary: nanosoc_chip_pads
*cmnV2LVS_LastTranslation: 1708338090 *cmnV2LVS_LastTranslation: 1708338090
ASIC/constraints.sdc
+ 1
− 1
View file @ 4fb0045d
...@@ -18,7 +18,7 @@ set_units -time ns; ...@@ -18,7 +18,7 @@ set_units -time ns;
set_units -capacitance pF; set_units -capacitance pF;
set EXTCLK_PERIOD 4.16667; set EXTCLK_PERIOD 4.16667;
set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD]; set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
set CLK_ERROR [expr 0.1*$EXTCLK_PERIOD]; set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
set INTER_CLOCK_UNCERTAINTY 0.1 set INTER_CLOCK_UNCERTAINTY 0.1
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK] create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
......
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