diff --git a/ASIC/44pin/Cadence/scripts/place_macros.tcl b/ASIC/44pin/Cadence/scripts/place_macros.tcl
index 54a9f805d37a8d44822e9fdebd17084ed7daa769..da6c92c653b441c2030e9c6dfe27ba841b187fd7 100644
--- a/ASIC/44pin/Cadence/scripts/place_macros.tcl
+++ b/ASIC/44pin/Cadence/scripts/place_macros.tcl
@@ -11,12 +11,14 @@
 # relative floorplan
 gui_set_draw_view fplan
 delete_relative_floorplan -all
-create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1  -4.8  1} -vertical_edge_separate {2  -2.4 2} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1  -4.8  1} -vertical_edge_separate {2  -2.4 2} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3  -12  1} -vertical_edge_separate {3  0  3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
 create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1  -4.8  1} -vertical_edge_separate {0  2.4  0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
 
+
 move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
 update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420}
 add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator  -min_gap 2.4
diff --git a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
index 68704dd15cd8e317c2abdc343a2bea3cc6df7356..4b8b44707496534fbd4c0338a3f86871a9485dbc 100644
--- a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
+++ b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
@@ -68,16 +68,29 @@ source filler.tcl
 ### Routing 
 source route.tcl 
 
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_early.rep
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_late.rep
 
 check_antenna
 write_db nanosoc_chip_pads
 
 delete_routes -net VDDIO
+delete_routes -net VSSIO
 source place_bondpads.tcl
 
+check_drc -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_drc.rep
+check_filler -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_filler.rep
+check_connectivity -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_connectivity.rep
+check_process_antenna -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_antenna.rep
 gui_show 
 
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_default_early.mtarpt
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_default_late.mtarpt
+set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_typical_early.mtarpt
+report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_typical_late.mtarpt
+set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
+
 write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
     -map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
     -lib_name DesignLib \
@@ -87,9 +100,12 @@ write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
 report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
 report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
 
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_late.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_early.rep
+
 set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical.rep
+report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_late.rep
+report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_early.rep
 
 set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
 
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
index 52c08f97f0f006bff8dcba4d364eac44525c7e41..e22aa4408f7717814536089a326b3582b2592cd4 100644
--- a/ASIC/44pin/Cadence/scripts/power_plan.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -57,7 +57,7 @@ set_db add_stripes_trim_antenna_back_to_shape none
 set_db add_stripes_spacing_type edge_to_edge
 set_db add_stripes_spacing_from_block 0
 set_db add_stripes_stripe_min_length stripe_width
-set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_top_layer M9
 set_db add_stripes_stacked_via_bottom_layer M4
 set_db add_stripes_via_using_exact_crossover_size false
 set_db add_stripes_split_vias false
@@ -65,7 +65,7 @@ set_db add_stripes_orthogonal_only true
 set_db add_stripes_allow_jog { padcore_ring  block_ring }
 set_db add_stripes_skip_via_on_pin {  standardcell }
 set_db add_stripes_skip_via_on_wire_shape {  noshape   }
-add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 2 -spacing 2 -set_to_set_distance 20 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit M9 -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit M9 -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
 
 deselect_obj -all
 
diff --git a/ASIC/44pin/Cadence/scripts/power_route.tcl b/ASIC/44pin/Cadence/scripts/power_route.tcl
index bf05e721f3b978bfc85e3b7aa790c38c7ccce5a8..46ef22319fdc340fff3b1693c5072e66f701d69b 100644
--- a/ASIC/44pin/Cadence/scripts/power_route.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_route.tcl
@@ -5,7 +5,7 @@
 # Author : Srimanth Tenneti 
 ##################################
 route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
-
+set_db route_special_via_connect_to_shape { padring stripe }
 route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
 route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
 
diff --git a/ASIC/44pin/Mentor/DRC b/ASIC/44pin/Mentor/DRC
new file mode 100644
index 0000000000000000000000000000000000000000..29d76a242246844adb1c027cfeb916427acaf7c3
--- /dev/null
+++ b/ASIC/44pin/Mentor/DRC
@@ -0,0 +1,17 @@
+*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/drc/calibre.drc
+*drcRulesFileLastLoad: 1708424374
+*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
+*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
+*drcLayoutPrimary: nanosoc_chip_pads
+*drcResultsFile: DRC_RES.db
+*drcResultsCheckText: 1
+*drcResultsCheckTextValue: ALL
+*drcCellName: 0
+*drcDRCMaxResultsAll: 1
+*drcSummaryFile: DRC.rep
+*drcActiveRecipe: Checks selected in the rules file
+*drcUserRecipes: {{Checks selected in the rules file}}
+*cmnResolution: 5
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
diff --git a/ASIC/44pin/Mentor/ERC b/ASIC/44pin/Mentor/ERC
new file mode 100644
index 0000000000000000000000000000000000000000..c364b62141ce10501fad3e61eca9d4a90614bfc8
--- /dev/null
+++ b/ASIC/44pin/Mentor/ERC
@@ -0,0 +1,17 @@
+*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/util/MAIN_DECK/CALIBRE_FLOW/nonUTM/DFM_LVS_RC_CAL_N65_ALRDL_noU_v16a.9m
+*drcRulesFileLastLoad: 1708424374
+*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
+*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc_fanis_20_02_24.gds
+*drcLayoutPrimary: nanosoc_chip_pads
+*drcResultsFile: DRC_RES.db
+*drcResultsCheckText: 1
+*drcResultsCheckTextValue: ALL
+*drcCellName: 0
+*drcDRCMaxResultsAll: 1
+*drcSummaryFile: DRC.rep
+*drcActiveRecipe: Checks selected in the rules file (Modified)
+*drcUserRecipes: {{Checks selected in the rules file (Modified)} {{group_unselect[1]} all {group_select[1]} rule_file}}
+*cmnResolution: 5
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
diff --git a/ASIC/44pin/Mentor/LVS b/ASIC/44pin/Mentor/LVS
index 4205367719242208a9246248385be11532dd2ea9..4c0d3a0ff354f9dcb2998fdbb1898bc168839e4c 100644
--- a/ASIC/44pin/Mentor/LVS
+++ b/ASIC/44pin/Mentor/LVS
@@ -1,8 +1,8 @@
 *lvsRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/lvs/calibre.lvs
-*lvsRunDir: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/./LVS
-*lvsLayoutPaths: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/nanosoc_srimanth_17_02_24.gds
+*lvsRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/LVS
+*lvsLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
 *lvsLayoutPrimary: nanosoc_chip_pads
-*lvsSourcePath: /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Srimanth/hell-fire-nanosoc/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v
+*lvsSourcePath: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v
 *lvsSourceSystem: VERILOG
 *lvsSourcePrimary: nanosoc_chip_pads
 *cmnV2LVS_LastTranslation: 1708338090
diff --git a/ASIC/constraints.sdc b/ASIC/constraints.sdc
index fa229e0e1eef54f0befa6a5fd429cb01943c4e83..024c31d325ac47a1df9732abb51f387806af9eb9 100644
--- a/ASIC/constraints.sdc
+++ b/ASIC/constraints.sdc
@@ -18,7 +18,7 @@ set_units -time ns;
 set_units -capacitance pF;
 set EXTCLK_PERIOD 4.16667;
 set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
-set CLK_ERROR [expr 0.1*$EXTCLK_PERIOD];
+set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
 set INTER_CLOCK_UNCERTAINTY 0.1
 
 create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]