flist/nanosoc_busmatrix.flist

@@ -16,8 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC BusMatrix IP search path    =============
--incdir $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
-
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v

lint/corstone101_ip.bb → hal/corstone101_ip.bb

@@ -57,4 +57,16 @@ bb_list
     // Exclude SRAM Model as Arm IP
     designunit = cmsdk_fpga_sram;
     file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v;
+    
+    // Exclude APB Slave Mux as Arm IP
+    designunit = cmsdk_apb_slave_mux;
+    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v;
+    
+    // Exclude APB Test slave as Arm IP
+    designunit = cmsdk_apb_test_slave;
+    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;
+    
+    // Exclude Pads
+    designunit = PAD_INOUT8MA_NOE;
+    file = $SOCLABS_GENERIC_LIB_TECH_DIR/pads/verilog/PAD_INOUT8MA_NOE.v;
 }
\ No newline at end of file

lint/nanosoc_ip.bb → hal/nanosoc_ip.bb

@@ -17,4 +17,8 @@ bb_list
     // Exclude Bus Matrix as Generated from Arm IP
     designunit = nanosoc_busmatrix_lite;
     file = $SOCLABS_NANOSOC_TECH_DIR/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v;
+    
+    // Temporarily Exclude SoCDebug
+    designunit = socdebug_ahb;
+    file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v;
 }
\ No newline at end of file

hal/nanosoc_ip.waive

+
+//-----------------------------------------------------------------------------
+// NanoSoC Lint Waivers 
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Wavier file for NanoSoC Chip Pads
+//-----------------------------------------------------------------------------
+lint_checking designunit = nanosoc_chip_pads
+{
+    // Combinatorial Wiring of outputs in top level of hierarchy
+    CBPAHI off;
+    
+    // Input/Output PIns decalred as inout so may have multiple drivers
+    GLTASR off;
+}
+
+lint_checking designunit = nanosoc_chip
+{
+    // Combinatorial Wiring of outputs in top level of hierarchy
+    CBPAHI off;
+}
+
+lint_checking designunit = nanosoc_ss_cpu
+{
+    // SYS Clock name renamed to just Clock
+    DIFCLK {"SYS_"} off;
+    
+    // Not Top-level in design_info
+    IOCOMB off;
+    TPOUNR off;
+    
+    // Some AHB Signals Unused 
+    USEPRT {"HBURST|HMASTLOCK"} off;
+}
+
+lint_checking designunit = nanosoc_ss_dma
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
+    
+    // DMAC 1 Currently tied off
+    ATLGLC off;
+    TIELOG {"DMAC_1"} off;
+    USEPRT {"DMAC_1"} off;
+}
+
+lint_checking designunit = nanosoc_ss_interconnect
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
+    
+    // System Width Parameters Unused (Interconnect generated from Arm Script)
+    USEPAR {"SYS_ADDR_W|SYS_DATA_W"} off;
+}
+
+lint_checking designunit = nanosoc_ss_debug
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
+    
+    // FT1248 can be a one-bit bus
+    ONPNSG {"FT_"} off;
+    
+    // Word Address Used only on APB
+    USEPRT {"DEBUG_PADDR"} off;   
+}
+
+lint_checking designunit = nanosoc_ss_expansion
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
+    
+    // FT1248 can be a one-bit bus
+    ONPNSG {"FT_"} off;
+    
+    // Word Address Used only on APB
+    USEPRT {"DEBUG_PADDR"} off;   
+}
+
+lint_checking designunit = nanosoc_ss_systemctrl
+{    
+    // Not Top-level in design_info
+    IOCOMB off;
+    TPOUNR off;
+    
+    // Doesn't recognise XTAL as Clock
+    CLKUCL {"XTAL"} off;
+    
+    // Resets have different names in Arm IP
+    DIFRST {"SYS_"} off;
+    
+    // Clocks have different names in Arm IP
+    DIFCLK {"SYS_"} off;
+    
+    // APB Write tied low
+    EXPIPC {"APB_DATA_W"} off;
+    
+    // APB Reset driven from SystemReset
+    RSTUCL off;
+    
+    // Unconnected Ports on Pin Mux and other peripherals
+    UNCONN {"p0_in|p1_in|P0|P1|_psel"} off;
+    
+    // TODO: UART Cross Over wiring Needs looking at
+    UNCONO {"p0_in|p1_in|uart|_psel"} off;
+    URDWIR {"uart0_rxd|uart1_rxd"} off;
+}
+
+lint_checking designunit = nanosoc_region_exp
+{    
+    // In Case of Default Slave, Read Data and IRQS and DRQs constant Assigned
+    TIELOG {"HRDATA|EXP_IRQ|EXP_DRQ"} off;
+    // Some AHB Signals wont be used in this case
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT|HWRITE|EXP_DLAST"} off;
+}
+
+lint_checking designunit = nanosoc_region_bootrom_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_imem_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_dmem_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_expram_l
+{   
+    // Some Bits of AHB Signals not Used
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_expram_h
+{   
+    // Some Bits of AHB Signals not Used
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_sysio
+{   
+    // Multiple Clock Domains in Module
+    MCKDMN off;
+    
+    // Combined Interrupts not connected
+    UNCONO {"COMBINT"} off;
+    UNCONN {"COMBINT"} off;
+    
+    // AHB signals unused
+    USEPRT {"HBURST|HMASTLOCK"} off;
+}
+
+lint_checking designunit = nanosoc_bootrom_cpu_0
+{
+    // Bootrom Clock name different to HCLK
+    DIFCLK {"HCLK"} off;
+    
+    // AHB Reponse Contant for Bootrom other than rdata
+    TIELOG {"HREADYOUT|HRESP"} off;
+    
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA"} off;
+}
+
+lint_checking designunit = bootrom
+{
+    // Combinatorial wiring through multiple levels of hierarchy to bootrom (wrappers)
+    CBPAHI off;
+    
+    // Default Case used for simulation
+    CDEFCV off;
+    
+    // Bootrom has no Reset
+    FFWNSR off;
+    
+    // States in Case Statements needs to be more than 40
+    LMTSTS off;
+}
+
+lint_checking designunit = nanosoc_clkctrl
+{
+    // Based Off of Arm IP
+    CBPAHI off;
+    NBGEND off;
+    
+    // Clocks Aliased (Clock control module)
+    DALIAS off;
+    DIFCLK off;
+    FDTHRU {"CLK"} off;
+    
+    // Reset Bypass select
+    GLTASR off;
+    
+    // Synchronous Reset
+    FRSTDF {"sync"} off;
+    RSTGNP off;
+    RSTINP {"prst"} off;
+    
+    // Bitwise Not Intended
+    LOGNEG {"reset|RST|RESET"} off;
+    
+    // Contains Synchronous and Asynchronous logic
+    SYNASN off;
+    
+    // Clock Gating Disable
+    TIELOG {"CLKEN"} off;
+    
+    // SYSRESETREQ crosses clock domain
+    CLKDMN {"nxt_prst"} off;
+    
+    // Combined Interrupts not connected
+    UNCONO {"COMBINT"} off;
+    
+    // pclkgen not used
+    URDWIR {"pclkgen"} off;
+    
+    // Some Ports Unused (Arm IP)
+    USEPRT off;
+}
+
+lint_checking designunit = nanosoc_pin_mux
+{   
+    // Arm IP Feedthrough on Pins
+    FDTHRU off;
+    IOCPIO off;
+    
+    // Inout Ports used
+    IOPNTA off;
+    
+    // Tristate Enable not driven by primary input
+    SLNOTP off;
+    
+    // Synopsys pragmas in RTL
+    TPRUSD off;
+    
+    // Inferred Tristate Correctly
+    TSBINF {"P0|P1"} off;
+    
+    // Contains logic other than Tri-States
+    TSMHOL off;
+    
+    // Some Ports Unused (Arm IP)
+    USEPRT {"altfunc"} off;
+
+}
+
+lint_checking designunit = nanosoc_sysctrl
+{
+    // Based off of Arm IP - bad pratice
+    CBPAHI off;
+    BOUINC off;
+    NBGEND off;
+    REVROP off;
+    
+    // Default Case still useful
+    CDEFCV off;
+    
+    // Parameters used in conditional Assignments
+    CONSTC {"BE"} off;
+    
+    // Bitwise Not Intended
+    LOGNEG {"reset|RST|RESET"} off;
+    
+    // Multiple Clocks
+    MULMCK off;
+    
+    // Contains Synchronous and Asynchronous logic
+    SYNASN off;
+    
+    // Some AHB Response Signals tied off
+    TIELOG {"HREADYOUT|HRESP"} off;
+    
+    // SYSRESETREQ crosses clock domain
+    CLKDMN {"reg_resetinfo"} off;
+    
+    // Not all Byte Strobes used and little endian data unused
+    URDREG {"byte_strobe|HWDATALE"} off;
+    
+    // Some AHB Signals unused
+    USEPRT {"HTRANS|HSIZE"} off;
+}
+
+lint_checking designunit = nanosoc_sysio_apb_ss
+{
+    // Based off of Arm IP with bad lint rules
+    CBPAHI off;
+    NBGEND off;
+    
+    // Parameters used in conditional Assignments
+    CONSTC {"BE"} off;
+    
+    // Bitwise And Intended
+    LOGAND {"endian"} off;
+    
+    // Bitwise Not Intended
+    LOGNEG {"RESET"} off;
+    
+    // Contains Synchronous and Asynchronous logic
+    SYNASN off;
+    
+    // Some Peripheral Signals Tied off
+    TIELOG {"uart|interrupt"} off;
+    
+    // BaudTick not connected
+    UNCONN {"BAUDTICK"} off;
+    
+    // APB Peripherals and interrupts tied off
+    UNCONO {"PPROT|PSEL|INT|BAUD"} off;
+    
+    // Some APB and Interrupts unused
+    URDWIR {"pprot|psel|int"} off;
+    
+    // TODO: Uart Crossover needs looking at
+    USEPRT {"uart0_rxd|uart1_rxd"} off;
+}
+
+lint_checking designunit = nanosoc_coresight_systable
+{
+    // Based off of Arm IP with bad lint rules
+    FFWNSR off; // No reset
+    NBGEND off; // No begin/end
+    
+    // Contains Synchronous and Asynchronous logic
+    SYNASN off;
+    
+    // Some AHB Response Signals tied off
+    TIELOG {"HREADYOUT|HRESP"} off;
+    
+    // Unequal Operands in assignment (Can't fix Arm IP)
+    ULCMPE {"PRESENT"} off;
+    
+    // Unused wire is unused
+    URDWIR {"unused"} off;
+    
+    // TODO: Uart Crossover needs looking at
+    USEPRT {"uart0_rxd|uart1_rxd"} off;
+}
+
+lint_checking designunit = nanosoc_sysio_decode
+{
+    // Some of AHB Address Unused
+    USEPRT {"haddr"} off;
+    
+}
\ No newline at end of file

makefile

@@ -37,6 +37,9 @@
 #
 #  Configurations
 
+# Include Lint Checks
+include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
+
 # Directory of Testcodes
 NANOSOC_SYSTEM_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/system
 NANOSOC_SW_DIR     ?= $(SOCLABS_NANOSOC_TECH_DIR)/software
@@ -90,8 +93,11 @@ ifeq ($(NANOSOC_EXPANSION_REGION),yes)
 	DEFINES_VC += +define+NANOSOC_EXPANSION_REGION
 endif
 
-# Simulator Command file to specify RTL source files
-TBENCH_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+# System Design Filelist
+DESIGN_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+# Testbench Filelist 
+TBENCH_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/system_tb.flist
 
 
 # Simulator type (mti/vcs/xm)
@@ -103,7 +109,11 @@ SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
 SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
 
 LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/nanosoc
-LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/lint
+LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/hal
+LINT_INFO_SLCOREM0_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal
+LINT_INFO_SLDMA230_DIR = $(SOCLABS_SLDMA230_TECH_DIR)/hal
+
+LINT_TOP = nanosoc_chip_pads
 
 # MTI option
 #DF#MTI_OPTIONS    = -novopt
@@ -119,6 +129,8 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)  $(ADP_OPTIONS)
 XMSIM_OPTIONS  = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
 XM_VC_OPTIONS  = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) 
 
+HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -design_info $(LINT_INFO_DIR)/corstone101_ip.bb -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb
+HAL_WAIVE     = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive
 
 # Debug Tester image
 DEBUGTESTER  = debugtester
@@ -189,10 +201,10 @@ compile_xm : bootrom
 	cd $(SIM_DIR); xmvlog  -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log
 	cd $(SIM_DIR); xmelab  -mess -f xmelab.args -access +r | tee -a compile_xm.log
 
-lint_xm: compile_xm
+lint_xm: bootrom
 	@rm -rf $(LINT_DIR) 
 	@mkdir -p $(LINT_DIR)
-	cd $(LINT_DIR); hal $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top nanosoc_chip -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -design_info $(LINT_INFO_DIR)/corstone101_ip.bb
+	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
 	
 # Note : If coverage is required, you can add -coverage all to xmelab
 

system/nanosoc_chip/chip/verilog/nanosoc_chip.v

@@ -86,7 +86,6 @@ module nanosoc_chip #(
   assign SYS_SCANENABLE  = 1'b0; 
   assign SYS_TESTMODE    = 1'b0;   
   assign INC_SCANINHCLK  = 1'b0; 
-  assign INC_SCANOUTHCLK = 1'b0;
   
   //--------------------------
   // Clock Wiring
@@ -187,7 +186,7 @@ module nanosoc_chip #(
       .P0_OUT(P0_OUT),
       .P0_OUTEN(P0_OUTEN),
       .P0_ALTFUNC(P0_ALTFUNC),
-      .P1_IN(P1_IN),
+      .P1_IN(P1_IN_MUX),
       .P1_OUT(P1_OUT),
       .P1_OUTEN(P1_OUTEN),
       .P1_ALTFUNC(P1_ALTFUNC),

system/nanosoc_control/verilog/nanosoc_pin_mux.v

@@ -75,28 +75,29 @@ module nanosoc_pin_mux (
     input  wire  [15:0]     p1_outen,
     input  wire  [15:0]     p1_altfunc,
 
-    // Processor debug interface
-    output wire             i_trst_n,
-    output wire             i_swditms,
-    output wire             i_swclktck,
-    output wire             i_tdi,
-    input  wire             i_tdo,
-    input  wire             i_tdoen_n,
-    input  wire             i_swdo,
-    input  wire             i_swdoen,
+    // // Processor debug interface
+    // output wire             i_trst_n,
+    // output wire             i_swditms,
+    // output wire             i_swclktck,
+    // output wire             i_tdi,
+    // input  wire             i_tdo,
+    // input  wire             i_tdoen_n,
+    // input  wire             i_swdo,
+    // input  wire             i_swdoen,
 
     // IO pads
     inout  wire  [15:0]     P0, // legacy
     inout  wire  [15:0]     P1, // legacy
 
     output wire  [15:0]     p1_out_mux,    //alt-function mux
-    output wire  [15:0]     p1_out_en_mux,  //alt-function mux
+    output wire  [15:0]     p1_out_en_mux  //alt-function mux
 
-    input  wire             nTRST, // Not needed if serial-wire debug is used
-    input  wire             TDI,   // Not needed if serial-wire debug is used
-    inout  wire             SWDIOTMS,
-    input  wire             SWCLKTCK,
-    output wire             TDO);   // Not needed if serial-wire debug is used
+    // input  wire             nTRST, // Not needed if serial-wire debug is used
+    // input  wire             TDI,   // Not needed if serial-wire debug is used
+    // inout  wire             SWDIOTMS,
+    // input  wire             SWCLKTCK,
+    // output wire             TDO);   // Not needed if serial-wire debug is used
+);
 
   //-------------------------------------------
   // Internal wires
@@ -232,13 +233,13 @@ module nanosoc_pin_mux (
   // Debug connections
   //-------------------------------------------
 
-  assign    i_trst_n     = nTRST;
-  assign    i_tdi        = TDI;
-  assign    i_swclktck   = SWCLKTCK;
-  assign    i_swditms    = SWDIOTMS;
+  // assign    i_trst_n     = nTRST;
+  // assign    i_tdi        = TDI;
+  // assign    i_swclktck   = SWCLKTCK;
+  // assign    i_swditms    = SWDIOTMS;
 
-  // Tristate buffers for debug output signals
-  bufif1 (SWDIOTMS, i_swdo, i_swdoen);
-  bufif0 (TDO,      i_tdo,  i_tdoen_n);
+  // // Tristate buffers for debug output signals
+  // bufif1 (SWDIOTMS, i_swdo, i_swdoen);
+  // bufif0 (TDO,      i_tdo,  i_tdoen_n);
 
   endmodule

system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v

@@ -13,7 +13,6 @@ module nanosoc_bootrom_cpu_0 #(
   parameter AW       = 10 // Address width
 )(
   input  wire          HCLK,      // Clock
-  input  wire          HRESETn,   // Reset
   input  wire          HSEL,      // Device select
   input  wire [AW-1:0] HADDR,     // Address
   input  wire    [1:0] HTRANS,    // Transfer control
@@ -25,14 +24,23 @@ module nanosoc_bootrom_cpu_0 #(
   output wire   [31:0] HRDATA,    // Read data output
   output wire          HRESP      // Device response (always OKAY)
 );
-
+  //------------------------
+  // Internal Wiring
+  //------------------------
+  wire   EN;
+  assign EN = HSEL & HTRANS[1] & HREADY & !HWRITE;
+  
+  //------------------------
+  // Bootrom Instantiation
+  //------------------------
   bootrom u_bootrom (
-    .CLK   (HCLK),
-    .EN    (HSEL & HTRANS[1] & HREADY & !HWRITE),
-    .ADDR  (HADDR[AW-1:2]),
-    .RDATA (HRDATA)
+    .CLK     (HCLK),
+    .EN      (EN),
+    .W_ADDR  (HADDR[AW-1:2]),
+    .RDATA   (HRDATA)
   );
   
+  // Output Signal Response Constant other than Data
   assign HREADYOUT = 1'b1;
   assign HRESP = 1'b0;
 

system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v

@@ -17,7 +17,6 @@ module nanosoc_region_bootrom_0 #(
     parameter    BOOTROM_ADDR_W = 10   // Size of Bootrom (Based on Address Width) - Default 1KB
   )(
     input  wire                   HCLK,       // Clock
-    input  wire                   HRESETn,    // Reset
 
     // AHB connection to Initiator
     input  wire                   HSEL,
@@ -38,7 +37,6 @@ module nanosoc_region_bootrom_0 #(
     .AW (BOOTROM_ADDR_W)  
   ) u_bootrom_cpu_0 (
     .HCLK             (HCLK),
-    .HRESETn          (HRESETn),
     .HSEL             (HSEL),
     .HADDR            (HADDR[9:0]),
     .HTRANS           (HTRANS),

system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v

@@ -36,8 +36,8 @@ module nanosoc_region_dmem_0 #(
 
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
+        .RAM_DATA_W (DMEM_RAM_DATA_W),
         .RAM_ADDR_W (DMEM_RAM_ADDR_W)
     ) u_dmem_0 (
         // AHB Inputs

system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v

@@ -65,12 +65,13 @@ module nanosoc_region_exp #(
         .HSEL         (HSEL),
         .HTRANS       (HTRANS),
         .HREADY       (HREADY),
-        .HREADYOUT    (HREADYOUTS),
-        .HRESP        (HRESPS)
+        .HREADYOUT    (HREADYOUT),
+        .HRESP        (HRESP)
     );
-    assign   HRDATA = 32'heaedeaed; // Tie off Expansion Address Expansion Data
-    assign   EXP_IRQ = 4'b0;
-    assign   EXP_DRQ = 2'b0;
+    
+    assign   HRDATA  = 32'heaedeaed; // Tie off Expansion Address Expansion Data
+    assign   EXP_IRQ = 4'd0;
+    assign   EXP_DRQ = 2'd0;
 `endif
 
 endmodule
\ No newline at end of file

system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v

@@ -37,9 +37,9 @@ module nanosoc_region_expram_h #(
     
     // AHB to SRAM bridge
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
-        .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W)
+        .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W),
+        .RAM_DATA_W (EXPRAM_H_RAM_DATA_W)
     ) u_expram_h (
         // AHB Inputs
         .HCLK       (HCLK),

system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v

@@ -37,9 +37,9 @@ module nanosoc_region_expram_l #(
     
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
-        .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W)
+        .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W),
+        .RAM_DATA_W (EXPRAM_L_RAM_DATA_W)
     ) u_expram_l (
         // AHB Inputs
         .HCLK       (HCLK),

system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v

@@ -38,9 +38,9 @@ module nanosoc_region_imem_0 #(
 
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
         .RAM_ADDR_W (IMEM_RAM_ADDR_W),
+        .RAM_DATA_W (IMEM_RAM_DATA_W),
         .FILENAME   (IMEM_RAM_FPGA_IMG)
     ) u_imem_0 (
         // AHB Inputs

system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v

@@ -19,7 +19,6 @@ module nanosoc_region_sysio #(
   )(
     input  wire                   FCLK,             // Free-running system clock
     input  wire                   PORESETn,         // Power-On-Reset reset (active-low)
-    input  wire                   TESTMODE,         // Reset bypass in scan test
     
     // AHB interface
     input  wire                   HCLK,             // AHB clock
@@ -75,7 +74,7 @@ module nanosoc_region_sysio #(
     // CPU power/reset control
     output wire                 REMAP_CTRL,       // REMAP control bit
     output wire                 APBACTIVE,        // APB bus active (for clock gating of PCLKG)
-    output wire                 SYSRESETREQ,      // Processor control - system reset request
+    input  wire                 SYSRESETREQ,      // Processor control - system reset request
     output wire                 WDOGRESETREQ,     // Watchdog reset request
     input  wire                 LOCKUP,           // Processor status - Locked up
     output wire                 LOCKUPRESET,      // System Controller cfg - reset if lockup

system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v

@@ -236,23 +236,20 @@ localparam  ARM_CMSDK_CM0_SYSCTRL_CID3        = {32'h000000B1}; // 0xFFC : CID 3
   // endian conversion
   always @(bigendian or reg_hsize or read_mux_le or HWDATA)
   begin
-    if ((bigendian)&(reg_hsize==2'b10))
-      begin
+    if ((bigendian)&&(reg_hsize==2'b10)) begin
       read_mux = {read_mux_le[ 7: 0],read_mux_le[15: 8],
                   read_mux_le[23:16],read_mux_le[31:24]};
       HWDATALE = {HWDATA[ 7: 0],HWDATA[15: 8],HWDATA[23:16],HWDATA[ 31:24]};
+    end else begin
+      if ((bigendian)&&(reg_hsize==2'b01)) begin
+        read_mux = {read_mux_le[23:16],read_mux_le[31:24],
+                    read_mux_le[ 7: 0],read_mux_le[15: 8]};
+        HWDATALE = {HWDATA[23:16],HWDATA[ 31:24],HWDATA[ 7: 0],HWDATA[15: 8]};
+      end else begin
+        read_mux = read_mux_le;
+        HWDATALE = HWDATA;
       end
-    else if ((bigendian)&(reg_hsize==2'b01))
-      begin
-      read_mux = {read_mux_le[23:16],read_mux_le[31:24],
-                  read_mux_le[ 7: 0],read_mux_le[15: 8]};
-      HWDATALE = {HWDATA[23:16],HWDATA[ 31:24],HWDATA[ 7: 0],HWDATA[15: 8]};
-      end
-    else
-      begin
-      read_mux = read_mux_le;
-      HWDATALE = HWDATA;
-      end
+    end
   end
   // ----------------------------------------------------------
   // Remap register

system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v

@@ -84,7 +84,7 @@ module nanosoc_coresight_systable
     // ------------------------------------------------------------
     // ROM Table Manufacturer, Part Number and Revision
     // ------------------------------------------------------------
-    parameter [6:0]    JEPID           = 7'b0000000, // JEP106 identity code
+    parameter [6:0]    JEPID           = 7'd0000000, // JEP106 identity code
     parameter [3:0]    JEPCONTINUATION = 4'h0,       // number of JEP106
                                                      // continuation codes
     parameter [11:0]   PARTNUMBER      = 12'h000,    // part number
@@ -155,10 +155,10 @@ module nanosoc_coresight_systable
    localparam [19:0] ENTRY3OFFSET = ENTRY3BASEADDR[31:12] - BASE[31:12];
 
    // Construct entries
-   localparam [31:0] ENTRY0 = { ENTRY0OFFSET, 10'b0, 1'b1, ENTRY0PRESENT!=0 };
-   localparam [31:0] ENTRY1 = { ENTRY1OFFSET, 10'b0, 1'b1, ENTRY1PRESENT!=0 };
-   localparam [31:0] ENTRY2 = { ENTRY2OFFSET, 10'b0, 1'b1, ENTRY2PRESENT!=0 };
-   localparam [31:0] ENTRY3 = { ENTRY3OFFSET, 10'b0, 1'b1, ENTRY3PRESENT!=0 };
+   localparam [31:0] ENTRY0 = { ENTRY0OFFSET, 10'd0, 1'b1, ENTRY0PRESENT!=0 };
+   localparam [31:0] ENTRY1 = { ENTRY1OFFSET, 10'd0, 1'b1, ENTRY1PRESENT!=0 };
+   localparam [31:0] ENTRY2 = { ENTRY2OFFSET, 10'd0, 1'b1, ENTRY2PRESENT!=0 };
+   localparam [31:0] ENTRY3 = { ENTRY3OFFSET, 10'd0, 1'b1, ENTRY3PRESENT!=0 };
 
 
    // ------------------------------------------------------------

system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v

@@ -17,7 +17,6 @@ module nanosoc_region_systable #(
     parameter    SYSTABLE_BASE = 32'hf000_0000 // Base Address for System ROM Table
 )(
     input  wire                     HCLK,       // Clock
-    input  wire                     HRESETn,    // Reset
 
     // AHB connection to Initiator
     input  wire                     HSEL,             // AHB region select

system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v

@@ -85,13 +85,13 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] BOOTROM_0_HPROT,        // Protection control
     input  wire   [31:0] BOOTROM_0_HWDATA,       // Write data
     input  wire          BOOTROM_0_HMASTLOCK,    // Locked Sequence
+    input  wire          BOOTROM_0_HREADY,       // HREADY feedback
     output wire   [31:0] BOOTROM_0_HRDATA,       // Read data bus
-    output wire          BOOTROM_0_HREADY,       // HREADY feedback
     output wire          BOOTROM_0_HRESP,        // Transfer response
     output wire          BOOTROM_0_HREADYOUT,    // AHB ready out
     
     // IMEM 0 AHB Lite port
-    input  wire          IMEM_0_HSEL,             // Select
+    input  wire          IMEM_0_HSEL,            // Select
     input  wire   [31:0] IMEM_0_HADDR,           // Address bus
     input  wire    [1:0] IMEM_0_HTRANS,          // Transfer type
     input  wire          IMEM_0_HWRITE,          // Transfer direction
@@ -100,8 +100,8 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] IMEM_0_HPROT,           // Protection control
     input  wire   [31:0] IMEM_0_HWDATA,          // Write data
     input  wire          IMEM_0_HMASTLOCK,       // Locked Sequence
+    input  wire          IMEM_0_HREADY,          // HREADY feedback
     output wire   [31:0] IMEM_0_HRDATA,          // Read data bus
-    output wire          IMEM_0_HREADY,          // HREADY feedback
     output wire          IMEM_0_HRESP,           // Transfer response
     output wire          IMEM_0_HREADYOUT,       // AHB ready out
     
@@ -115,8 +115,8 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] DMEM_0_HPROT,           // Protection control
     input  wire   [31:0] DMEM_0_HWDATA,          // Write data
     input  wire          DMEM_0_HMASTLOCK,       // Locked Sequence
+    input  wire          DMEM_0_HREADY,          // HREADY feedback
     output wire   [31:0] DMEM_0_HRDATA,          // Read data bus
-    output wire          DMEM_0_HREADY,          // HREADY feedback
     output wire          DMEM_0_HRESP,           // Transfer response
     output wire          DMEM_0_HREADYOUT,       // AHB ready out
 
@@ -213,9 +213,8 @@ module nanosoc_ss_cpu #(
         .SYS_DATA_W      (SYS_DATA_W),
         .BOOTROM_ADDR_W  (BOOTROM_ADDR_W)
     ) u_region_bootrom_0 (
-        // Clock and Reset
+        // Clock (No Reset on Bootrom)
         .HCLK(SYS_HCLK),
-        .HRESETn(SYS_HRESETn),
 
         // AHB connection to Initiator
         .HSEL(BOOTROM_0_HSEL),

system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v

@@ -14,6 +14,9 @@ module nanosoc_ss_debug #(
     parameter         SYS_ADDR_W    = 32,  // System Address Width
     parameter         SYS_DATA_W    = 32,  // System Data Width
     
+    parameter         APB_ADDR_W    = 12,  // APB Address Width
+    parameter         APB_DATA_W    = 32,  // APB Data Width
+    
     // SoCDebug Parameters
     parameter         PROMPT_CHAR   = "]",
     parameter integer FT1248_WIDTH	= 1, // FTDI Interface 1,2,4 width supported
@@ -28,25 +31,25 @@ module nanosoc_ss_debug #(
     input  wire                     SYS_PRESETn,
     
     // AHB-lite Master Interface - ADP
-    output wire              [31:0] DEBUG_HADDR,
+    output wire    [SYS_ADDR_W-1:0] DEBUG_HADDR,
     output wire              [ 2:0] DEBUG_HBURST,
     output wire                     DEBUG_HMASTLOCK,
     output wire              [ 3:0] DEBUG_HPROT,
     output wire              [ 2:0] DEBUG_HSIZE,
     output wire              [ 1:0] DEBUG_HTRANS,
-    output wire              [31:0] DEBUG_HWDATA,
+    output wire    [SYS_DATA_W-1:0] DEBUG_HWDATA,
     output wire                     DEBUG_HWRITE,
-    input  wire              [31:0] DEBUG_HRDATA,
+    input  wire    [SYS_DATA_W-1:0] DEBUG_HRDATA,
     input  wire                     DEBUG_HREADY,
     input  wire                     DEBUG_HRESP,
     
     // APB Slave Interface - USRT
     input  wire                     DEBUG_PSEL,      // Device select
-    input  wire              [11:0] DEBUG_PADDR,     // Address
+    input  wire    [APB_ADDR_W-1:0] DEBUG_PADDR,     // Address
     input  wire                     DEBUG_PENABLE,   // Transfer control
     input  wire                     DEBUG_PWRITE,    // Write control
-    input  wire              [31:0] DEBUG_PWDATA,    // Write data
-    output wire              [31:0] DEBUG_PRDATA,    // Read data
+    input  wire    [APB_DATA_W-1:0] DEBUG_PWDATA,    // Write data
+    output wire    [APB_DATA_W-1:0] DEBUG_PRDATA,    // Read data
     output wire                     DEBUG_PREADY,    // Device ready
     output wire                     DEBUG_PSLVERR,   // Device error response
     
@@ -63,7 +66,10 @@ module nanosoc_ss_debug #(
     output wire               [7:0] GPO8,
     input  wire               [7:0] GPI8
 );
-
+    
+    //---------------------------
+    // SoCDebug Instantiation
+    //---------------------------
     socdebug_ahb #(
         .PROMPT_CHAR(PROMPT_CHAR),
         .FT1248_WIDTH(FT1248_WIDTH),
@@ -90,7 +96,7 @@ module nanosoc_ss_debug #(
         .PCLKG(SYS_PCLKG),
         .PRESETn(SYS_PRESETn),
         .PSEL_i(DEBUG_PSEL),
-        .PADDR_i(DEBUG_PADDR[11:2]),
+        .PADDR_i(DEBUG_PADDR[APB_ADDR_W-1:2]),
         .PENABLE_i(DEBUG_PENABLE),
         .PWRITE_i(DEBUG_PWRITE),
         .PWDATA_i(DEBUG_PWDATA),