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Commit 3c33f4ae authored by dam1n19's avatar dam1n19
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Modified Bootrom generation and Removed SWD Pins from Pin Mux

parent 6d25a402
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_control/verilog/nanosoc_pin_mux.v
+ 23
− 22
View file @ 3c33f4ae
...@@ -75,28 +75,29 @@ module nanosoc_pin_mux ( ...@@ -75,28 +75,29 @@ module nanosoc_pin_mux (
input wire [15:0] p1_outen, input wire [15:0] p1_outen,
input wire [15:0] p1_altfunc, input wire [15:0] p1_altfunc,
// Processor debug interface // // Processor debug interface
output wire i_trst_n, // output wire i_trst_n,
output wire i_swditms, // output wire i_swditms,
output wire i_swclktck, // output wire i_swclktck,
output wire i_tdi, // output wire i_tdi,
input wire i_tdo, // input wire i_tdo,
input wire i_tdoen_n, // input wire i_tdoen_n,
input wire i_swdo, // input wire i_swdo,
input wire i_swdoen, // input wire i_swdoen,
// IO pads // IO pads
inout wire [15:0] P0, // legacy inout wire [15:0] P0, // legacy
inout wire [15:0] P1, // legacy inout wire [15:0] P1, // legacy
output wire [15:0] p1_out_mux, //alt-function mux output wire [15:0] p1_out_mux, //alt-function mux
output wire [15:0] p1_out_en_mux, //alt-function mux output wire [15:0] p1_out_en_mux //alt-function mux
input wire nTRST, // Not needed if serial-wire debug is used // input wire nTRST, // Not needed if serial-wire debug is used
input wire TDI, // Not needed if serial-wire debug is used // input wire TDI, // Not needed if serial-wire debug is used
inout wire SWDIOTMS, // inout wire SWDIOTMS,
input wire SWCLKTCK, // input wire SWCLKTCK,
output wire TDO); // Not needed if serial-wire debug is used // output wire TDO); // Not needed if serial-wire debug is used
);
//------------------------------------------- //-------------------------------------------
// Internal wires // Internal wires
...@@ -232,13 +233,13 @@ module nanosoc_pin_mux ( ...@@ -232,13 +233,13 @@ module nanosoc_pin_mux (
// Debug connections // Debug connections
//------------------------------------------- //-------------------------------------------
assign i_trst_n = nTRST; // assign i_trst_n = nTRST;
assign i_tdi = TDI; // assign i_tdi = TDI;
assign i_swclktck = SWCLKTCK; // assign i_swclktck = SWCLKTCK;
assign i_swditms = SWDIOTMS; // assign i_swditms = SWDIOTMS;
// Tristate buffers for debug output signals // // Tristate buffers for debug output signals
bufif1 (SWDIOTMS, i_swdo, i_swdoen); // bufif1 (SWDIOTMS, i_swdo, i_swdoen);
bufif0 (TDO, i_tdo, i_tdoen_n); // bufif0 (TDO, i_tdo, i_tdoen_n);
endmodule endmodule
system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+ 14
− 14
View file @ 3c33f4ae
...@@ -204,26 +204,26 @@ module nanosoc_ss_systemctrl #( ...@@ -204,26 +204,26 @@ module nanosoc_ss_systemctrl #(
.p1_altfunc (P1_ALTFUNC), .p1_altfunc (P1_ALTFUNC),
// Debug // Debug
.i_trst_n ( ), // .i_trst_n ( ),
.i_swditms ( ), //i_swditms), // .i_swditms ( ), //i_swditms),
.i_swclktck ( ), //i_swclktck), // .i_swclktck ( ), //i_swclktck),
.i_tdi ( ), // .i_tdi ( ),
.i_tdo ( ), // .i_tdo ( ),
.i_tdoen_n ( ), // .i_tdoen_n ( ),
.i_swdo ( ), // .i_swdo ( ),
.i_swdoen ( ), // .i_swdoen ( ),
// IO pads // IO pads
.p1_out_mux (P1_OUT_MUX), .p1_out_mux (P1_OUT_MUX),
.p1_out_en_mux (P1_OUT_EN_MUX), .p1_out_en_mux (P1_OUT_EN_MUX),
.P0 ( ), //P0), .P0 ( ), //P0),
.P1 ( ), //P1), .P1 ( ) //P1),
.nTRST (1'b1), // Not needed if serial-wire debug is used // .nTRST (1'b1), // Not needed if serial-wire debug is used
.TDI (1'b0), // Not needed if serial-wire debug is used // .TDI (1'b0), // Not needed if serial-wire debug is used
.SWDIOTMS ( ), //SWDIOTMS), // .SWDIOTMS ( ), //SWDIOTMS),
.SWCLKTCK ( ), //SWCLKTCK), // .SWCLKTCK ( ), //SWCLKTCK),
.TDO ( ) // Not needed if serial-wire debug is used // .TDO ( ) // Not needed if serial-wire debug is used
); );
// ------------------------------- // -------------------------------
......
system/nanosoc_system/verilog/nanosoc_system.v
+ 17
− 14
View file @ 3c33f4ae
...@@ -144,6 +144,13 @@ module nanosoc_system #( ...@@ -144,6 +144,13 @@ module nanosoc_system #(
wire [APB_ADDR_W-1:0] SYSIO_PADDR; wire [APB_ADDR_W-1:0] SYSIO_PADDR;
wire [APB_DATA_W-1:0] SYSIO_PWDATA; wire [APB_DATA_W-1:0] SYSIO_PWDATA;
// CPU sideband signalling - TO CPU Subsystem
wire [31:0] SYS_APB_IRQ; // apbsubsys_interrupt;
wire [15:0] SYS_GPIO0_IRQ; // GPIO 0 IRQs
wire [15:0] SYS_GPIO1_IRQ; // GPIO 0 IRQs
wire SYS_NMI; // watchdog_interrupt;
//-------------------------- //--------------------------
// CPU Subsystem // CPU Subsystem
//-------------------------- //--------------------------
...@@ -319,7 +326,7 @@ module nanosoc_system #( ...@@ -319,7 +326,7 @@ module nanosoc_system #(
.DMEM_0_HREADYOUT(DMEM_0_HREADYOUT), .DMEM_0_HREADYOUT(DMEM_0_HREADYOUT),
// CPU Sideband signalling // CPU Sideband signalling
.CPU_0_NMI(CPU_0_NMI), .CPU_0_NMI(SYS_NMI),
.CPU_0_IRQ(CPU_0_IRQ), .CPU_0_IRQ(CPU_0_IRQ),
.CPU_0_TXEV(CPU_0_TXEV), .CPU_0_TXEV(CPU_0_TXEV),
.CPU_0_RXEV(CPU_0_RXEV), .CPU_0_RXEV(CPU_0_RXEV),
...@@ -752,11 +759,7 @@ module nanosoc_system #( ...@@ -752,11 +759,7 @@ module nanosoc_system #(
wire SYSTABLE_HRESP; // AHB response wire SYSTABLE_HRESP; // AHB response
wire SYSTABLE_HREADYOUT; // AHB ready out wire SYSTABLE_HREADYOUT; // AHB ready out
// CPU sideband signalling - TO CPU Subsystem
wire SYS_NMI; // watchdog_interrupt;
wire [31:0] SYS_APB_IRQ; // apbsubsys_interrupt;
wire [15:0] SYS_GPIO0_IRQ; // GPIO 0 IRQs
wire [15:0] SYS_GPIO1_IRQ; // GPIO 0 IRQs
// Bus Matrix Remap Control - To Interconnect Subsystem // Bus Matrix Remap Control - To Interconnect Subsystem
wire SYSIO_REMAP_CTRL; // REMAP control bit wire SYSIO_REMAP_CTRL; // REMAP control bit
...@@ -1003,7 +1006,7 @@ module nanosoc_system #( ...@@ -1003,7 +1006,7 @@ module nanosoc_system #(
.BOOTROM_0_HPROT(BOOTROM_0_HPROT), .BOOTROM_0_HPROT(BOOTROM_0_HPROT),
.BOOTROM_0_HWDATA(BOOTROM_0_HWDATA), .BOOTROM_0_HWDATA(BOOTROM_0_HWDATA),
.BOOTROM_0_HMASTLOCK(BOOTROM_0_HMASTLOCK), .BOOTROM_0_HMASTLOCK(BOOTROM_0_HMASTLOCK),
.BOOTROM_0_HREADYMUX(BOOTROM_0_HREADYMUX), .BOOTROM_0_HREADYMUX(BOOTROM_0_HREADY),
// CPU 0 Instruction Memory Region Slave Port // CPU 0 Instruction Memory Region Slave Port
.IMEM_0_HRDATA(IMEM_0_HRDATA), .IMEM_0_HRDATA(IMEM_0_HRDATA),
...@@ -1018,7 +1021,7 @@ module nanosoc_system #( ...@@ -1018,7 +1021,7 @@ module nanosoc_system #(
.IMEM_0_HPROT(IMEM_0_HPROT), .IMEM_0_HPROT(IMEM_0_HPROT),
.IMEM_0_HWDATA(IMEM_0_HWDATA), .IMEM_0_HWDATA(IMEM_0_HWDATA),
.IMEM_0_HMASTLOCK(IMEM_0_HMASTLOCK), .IMEM_0_HMASTLOCK(IMEM_0_HMASTLOCK),
.IMEM_0_HREADYMUX(IMEM_0_HREADYMUX), .IMEM_0_HREADYMUX(IMEM_0_HREADY),
// CPU 0 Data Memory Region Slave Port // CPU 0 Data Memory Region Slave Port
.DMEM_0_HRDATA(DMEM_0_HRDATA), .DMEM_0_HRDATA(DMEM_0_HRDATA),
...@@ -1033,7 +1036,7 @@ module nanosoc_system #( ...@@ -1033,7 +1036,7 @@ module nanosoc_system #(
.DMEM_0_HPROT(DMEM_0_HPROT), .DMEM_0_HPROT(DMEM_0_HPROT),
.DMEM_0_HWDATA(DMEM_0_HWDATA), .DMEM_0_HWDATA(DMEM_0_HWDATA),
.DMEM_0_HMASTLOCK(DMEM_0_HMASTLOCK), .DMEM_0_HMASTLOCK(DMEM_0_HMASTLOCK),
.DMEM_0_HREADYMUX(DMEM_0_HREADYMUX), .DMEM_0_HREADYMUX(DMEM_0_HREADY),
// System Peripheral Region Slave Port // System Peripheral Region Slave Port
.SYSIO_HRDATA(SYSIO_HRDATA), .SYSIO_HRDATA(SYSIO_HRDATA),
...@@ -1048,7 +1051,7 @@ module nanosoc_system #( ...@@ -1048,7 +1051,7 @@ module nanosoc_system #(
.SYSIO_HPROT(SYSIO_HPROT), .SYSIO_HPROT(SYSIO_HPROT),
.SYSIO_HWDATA(SYSIO_HWDATA), .SYSIO_HWDATA(SYSIO_HWDATA),
.SYSIO_HMASTLOCK(SYSIO_HMASTLOCK), .SYSIO_HMASTLOCK(SYSIO_HMASTLOCK),
.SYSIO_HREADYMUX(SYSIO_HREADYMUX), .SYSIO_HREADYMUX(SYSIO_HREADY),
// Expansion Memory Low Region Slave Port // Expansion Memory Low Region Slave Port
.EXPRAM_L_HRDATA(EXPRAM_L_HRDATA), .EXPRAM_L_HRDATA(EXPRAM_L_HRDATA),
...@@ -1063,7 +1066,7 @@ module nanosoc_system #( ...@@ -1063,7 +1066,7 @@ module nanosoc_system #(
.EXPRAM_L_HPROT(EXPRAM_L_HPROT), .EXPRAM_L_HPROT(EXPRAM_L_HPROT),
.EXPRAM_L_HWDATA(EXPRAM_L_HWDATA), .EXPRAM_L_HWDATA(EXPRAM_L_HWDATA),
.EXPRAM_L_HMASTLOCK(EXPRAM_L_HMASTLOCK), .EXPRAM_L_HMASTLOCK(EXPRAM_L_HMASTLOCK),
.EXPRAM_L_HREADYMUX(EXPRAM_L_HREADYMUX), .EXPRAM_L_HREADYMUX(EXPRAM_L_HREADY),
// Expansion Memory High Region Slave Port // Expansion Memory High Region Slave Port
.EXPRAM_H_HRDATA(EXPRAM_H_HRDATA), .EXPRAM_H_HRDATA(EXPRAM_H_HRDATA),
...@@ -1078,7 +1081,7 @@ module nanosoc_system #( ...@@ -1078,7 +1081,7 @@ module nanosoc_system #(
.EXPRAM_H_HPROT(EXPRAM_H_HPROT), .EXPRAM_H_HPROT(EXPRAM_H_HPROT),
.EXPRAM_H_HWDATA(EXPRAM_H_HWDATA), .EXPRAM_H_HWDATA(EXPRAM_H_HWDATA),
.EXPRAM_H_HMASTLOCK(EXPRAM_H_HMASTLOCK), .EXPRAM_H_HMASTLOCK(EXPRAM_H_HMASTLOCK),
.EXPRAM_H_HREADYMUX(EXPRAM_H_HREADYMUX), .EXPRAM_H_HREADYMUX(EXPRAM_H_HREADY),
// Expansion Region Slave Port // Expansion Region Slave Port
.EXP_HRDATA(EXP_HRDATA), .EXP_HRDATA(EXP_HRDATA),
...@@ -1093,7 +1096,7 @@ module nanosoc_system #( ...@@ -1093,7 +1096,7 @@ module nanosoc_system #(
.EXP_HPROT(EXP_HPROT), .EXP_HPROT(EXP_HPROT),
.EXP_HWDATA(EXP_HWDATA), .EXP_HWDATA(EXP_HWDATA),
.EXP_HMASTLOCK(EXP_HMASTLOCK), .EXP_HMASTLOCK(EXP_HMASTLOCK),
.EXP_HREADYMUX(EXP_HREADYMUX), .EXP_HREADYMUX(EXP_HREADY),
// System ROM Table Region Slave Port // System ROM Table Region Slave Port
.SYSTABLE_HRDATA(SYSTABLE_HRDATA), .SYSTABLE_HRDATA(SYSTABLE_HRDATA),
...@@ -1108,7 +1111,7 @@ module nanosoc_system #( ...@@ -1108,7 +1111,7 @@ module nanosoc_system #(
.SYSTABLE_HPROT(SYSTABLE_HPROT), .SYSTABLE_HPROT(SYSTABLE_HPROT),
.SYSTABLE_HWDATA(SYSTABLE_HWDATA), .SYSTABLE_HWDATA(SYSTABLE_HWDATA),
.SYSTABLE_HMASTLOCK(SYSTABLE_HMASTLOCK), .SYSTABLE_HMASTLOCK(SYSTABLE_HMASTLOCK),
.SYSTABLE_HREADYMUX(SYSTABLE_HREADYMUX) .SYSTABLE_HREADYMUX(SYSTABLE_HREADY)
); );
endmodule endmodule
\ No newline at end of file
slcorem0_tech @ 2e3ae3bc
Compare 40a7506c...2e3ae3bc
Subproject commit 40a7506cd234ef65f3f7094d2e4ae9f349f5f969 Subproject commit 2e3ae3bc669358a1ee423bb8f2af6e8e5c628966
testcodes/bootloader/bootrom_gen.py
+ 4
− 5
View file @ 3c33f4ae
...@@ -32,10 +32,9 @@ module bootrom ( ...@@ -32,10 +32,9 @@ module bootrom (
input wire EN, input wire EN,
input wire [$address_width:2] ADDR, input wire [$address_width:2] ADDR,
output reg [31:0] RDATA ); output reg [31:0] RDATA );
reg [$address_width:2] addr_r; always @(posedge CLK)
always @(posedge CLK) if (EN) addr_r <= ADDR; if (EN)
always @(addr_r) case(ADDR[$address_width:2])
case(addr_r[$address_width:2])
""" """
v_template_foot = """ default : RDATA <= 32'h0; v_template_foot = """ default : RDATA <= 32'h0;
......
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