From 3c33f4ae4c02ceec192be6d1aff13876e711c829 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 15:22:11 +0100
Subject: [PATCH] Modified Bootrom generation and Removed SWD Pins from Pin Mux
---
.../nanosoc_control/verilog/nanosoc_pin_mux.v | 45 ++++++++++---------
.../verilog/nanosoc_ss_systemctrl.v | 28 ++++++------
.../nanosoc_system/verilog/nanosoc_system.v | 31 +++++++------
system/slcorem0_tech | 2 +-
testcodes/bootloader/bootrom_gen.py | 9 ++--
5 files changed, 59 insertions(+), 56 deletions(-)
diff --git a/system/nanosoc_control/verilog/nanosoc_pin_mux.v b/system/nanosoc_control/verilog/nanosoc_pin_mux.v
index c9e4e97..96049ac 100644
--- a/system/nanosoc_control/verilog/nanosoc_pin_mux.v
+++ b/system/nanosoc_control/verilog/nanosoc_pin_mux.v
@@ -75,28 +75,29 @@ module nanosoc_pin_mux (
input wire [15:0] p1_outen,
input wire [15:0] p1_altfunc,
- // Processor debug interface
- output wire i_trst_n,
- output wire i_swditms,
- output wire i_swclktck,
- output wire i_tdi,
- input wire i_tdo,
- input wire i_tdoen_n,
- input wire i_swdo,
- input wire i_swdoen,
+ // // Processor debug interface
+ // output wire i_trst_n,
+ // output wire i_swditms,
+ // output wire i_swclktck,
+ // output wire i_tdi,
+ // input wire i_tdo,
+ // input wire i_tdoen_n,
+ // input wire i_swdo,
+ // input wire i_swdoen,
// IO pads
inout wire [15:0] P0, // legacy
inout wire [15:0] P1, // legacy
output wire [15:0] p1_out_mux, //alt-function mux
- output wire [15:0] p1_out_en_mux, //alt-function mux
+ output wire [15:0] p1_out_en_mux //alt-function mux
- input wire nTRST, // Not needed if serial-wire debug is used
- input wire TDI, // Not needed if serial-wire debug is used
- inout wire SWDIOTMS,
- input wire SWCLKTCK,
- output wire TDO); // Not needed if serial-wire debug is used
+ // input wire nTRST, // Not needed if serial-wire debug is used
+ // input wire TDI, // Not needed if serial-wire debug is used
+ // inout wire SWDIOTMS,
+ // input wire SWCLKTCK,
+ // output wire TDO); // Not needed if serial-wire debug is used
+);
//-------------------------------------------
// Internal wires
@@ -232,13 +233,13 @@ module nanosoc_pin_mux (
// Debug connections
//-------------------------------------------
- assign i_trst_n = nTRST;
- assign i_tdi = TDI;
- assign i_swclktck = SWCLKTCK;
- assign i_swditms = SWDIOTMS;
+ // assign i_trst_n = nTRST;
+ // assign i_tdi = TDI;
+ // assign i_swclktck = SWCLKTCK;
+ // assign i_swditms = SWDIOTMS;
- // Tristate buffers for debug output signals
- bufif1 (SWDIOTMS, i_swdo, i_swdoen);
- bufif0 (TDO, i_tdo, i_tdoen_n);
+ // // Tristate buffers for debug output signals
+ // bufif1 (SWDIOTMS, i_swdo, i_swdoen);
+ // bufif0 (TDO, i_tdo, i_tdoen_n);
endmodule
diff --git a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 24e823b..3e4a7c5 100644
--- a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -204,26 +204,26 @@ module nanosoc_ss_systemctrl #(
.p1_altfunc (P1_ALTFUNC),
// Debug
- .i_trst_n ( ),
- .i_swditms ( ), //i_swditms),
- .i_swclktck ( ), //i_swclktck),
- .i_tdi ( ),
- .i_tdo ( ),
- .i_tdoen_n ( ),
- .i_swdo ( ),
- .i_swdoen ( ),
+ // .i_trst_n ( ),
+ // .i_swditms ( ), //i_swditms),
+ // .i_swclktck ( ), //i_swclktck),
+ // .i_tdi ( ),
+ // .i_tdo ( ),
+ // .i_tdoen_n ( ),
+ // .i_swdo ( ),
+ // .i_swdoen ( ),
// IO pads
.p1_out_mux (P1_OUT_MUX),
.p1_out_en_mux (P1_OUT_EN_MUX),
.P0 ( ), //P0),
- .P1 ( ), //P1),
+ .P1 ( ) //P1),
- .nTRST (1'b1), // Not needed if serial-wire debug is used
- .TDI (1'b0), // Not needed if serial-wire debug is used
- .SWDIOTMS ( ), //SWDIOTMS),
- .SWCLKTCK ( ), //SWCLKTCK),
- .TDO ( ) // Not needed if serial-wire debug is used
+ // .nTRST (1'b1), // Not needed if serial-wire debug is used
+ // .TDI (1'b0), // Not needed if serial-wire debug is used
+ // .SWDIOTMS ( ), //SWDIOTMS),
+ // .SWCLKTCK ( ), //SWCLKTCK),
+ // .TDO ( ) // Not needed if serial-wire debug is used
);
// -------------------------------
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index 24b2146..43670cb 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -144,6 +144,13 @@ module nanosoc_system #(
wire [APB_ADDR_W-1:0] SYSIO_PADDR;
wire [APB_DATA_W-1:0] SYSIO_PWDATA;
+ // CPU sideband signalling - TO CPU Subsystem
+ wire [31:0] SYS_APB_IRQ; // apbsubsys_interrupt;
+ wire [15:0] SYS_GPIO0_IRQ; // GPIO 0 IRQs
+ wire [15:0] SYS_GPIO1_IRQ; // GPIO 0 IRQs
+ wire SYS_NMI; // watchdog_interrupt;
+
+
//--------------------------
// CPU Subsystem
//--------------------------
@@ -319,7 +326,7 @@ module nanosoc_system #(
.DMEM_0_HREADYOUT(DMEM_0_HREADYOUT),
// CPU Sideband signalling
- .CPU_0_NMI(CPU_0_NMI),
+ .CPU_0_NMI(SYS_NMI),
.CPU_0_IRQ(CPU_0_IRQ),
.CPU_0_TXEV(CPU_0_TXEV),
.CPU_0_RXEV(CPU_0_RXEV),
@@ -752,11 +759,7 @@ module nanosoc_system #(
wire SYSTABLE_HRESP; // AHB response
wire SYSTABLE_HREADYOUT; // AHB ready out
- // CPU sideband signalling - TO CPU Subsystem
- wire SYS_NMI; // watchdog_interrupt;
- wire [31:0] SYS_APB_IRQ; // apbsubsys_interrupt;
- wire [15:0] SYS_GPIO0_IRQ; // GPIO 0 IRQs
- wire [15:0] SYS_GPIO1_IRQ; // GPIO 0 IRQs
+
// Bus Matrix Remap Control - To Interconnect Subsystem
wire SYSIO_REMAP_CTRL; // REMAP control bit
@@ -1003,7 +1006,7 @@ module nanosoc_system #(
.BOOTROM_0_HPROT(BOOTROM_0_HPROT),
.BOOTROM_0_HWDATA(BOOTROM_0_HWDATA),
.BOOTROM_0_HMASTLOCK(BOOTROM_0_HMASTLOCK),
- .BOOTROM_0_HREADYMUX(BOOTROM_0_HREADYMUX),
+ .BOOTROM_0_HREADYMUX(BOOTROM_0_HREADY),
// CPU 0 Instruction Memory Region Slave Port
.IMEM_0_HRDATA(IMEM_0_HRDATA),
@@ -1018,7 +1021,7 @@ module nanosoc_system #(
.IMEM_0_HPROT(IMEM_0_HPROT),
.IMEM_0_HWDATA(IMEM_0_HWDATA),
.IMEM_0_HMASTLOCK(IMEM_0_HMASTLOCK),
- .IMEM_0_HREADYMUX(IMEM_0_HREADYMUX),
+ .IMEM_0_HREADYMUX(IMEM_0_HREADY),
// CPU 0 Data Memory Region Slave Port
.DMEM_0_HRDATA(DMEM_0_HRDATA),
@@ -1033,7 +1036,7 @@ module nanosoc_system #(
.DMEM_0_HPROT(DMEM_0_HPROT),
.DMEM_0_HWDATA(DMEM_0_HWDATA),
.DMEM_0_HMASTLOCK(DMEM_0_HMASTLOCK),
- .DMEM_0_HREADYMUX(DMEM_0_HREADYMUX),
+ .DMEM_0_HREADYMUX(DMEM_0_HREADY),
// System Peripheral Region Slave Port
.SYSIO_HRDATA(SYSIO_HRDATA),
@@ -1048,7 +1051,7 @@ module nanosoc_system #(
.SYSIO_HPROT(SYSIO_HPROT),
.SYSIO_HWDATA(SYSIO_HWDATA),
.SYSIO_HMASTLOCK(SYSIO_HMASTLOCK),
- .SYSIO_HREADYMUX(SYSIO_HREADYMUX),
+ .SYSIO_HREADYMUX(SYSIO_HREADY),
// Expansion Memory Low Region Slave Port
.EXPRAM_L_HRDATA(EXPRAM_L_HRDATA),
@@ -1063,7 +1066,7 @@ module nanosoc_system #(
.EXPRAM_L_HPROT(EXPRAM_L_HPROT),
.EXPRAM_L_HWDATA(EXPRAM_L_HWDATA),
.EXPRAM_L_HMASTLOCK(EXPRAM_L_HMASTLOCK),
- .EXPRAM_L_HREADYMUX(EXPRAM_L_HREADYMUX),
+ .EXPRAM_L_HREADYMUX(EXPRAM_L_HREADY),
// Expansion Memory High Region Slave Port
.EXPRAM_H_HRDATA(EXPRAM_H_HRDATA),
@@ -1078,7 +1081,7 @@ module nanosoc_system #(
.EXPRAM_H_HPROT(EXPRAM_H_HPROT),
.EXPRAM_H_HWDATA(EXPRAM_H_HWDATA),
.EXPRAM_H_HMASTLOCK(EXPRAM_H_HMASTLOCK),
- .EXPRAM_H_HREADYMUX(EXPRAM_H_HREADYMUX),
+ .EXPRAM_H_HREADYMUX(EXPRAM_H_HREADY),
// Expansion Region Slave Port
.EXP_HRDATA(EXP_HRDATA),
@@ -1093,7 +1096,7 @@ module nanosoc_system #(
.EXP_HPROT(EXP_HPROT),
.EXP_HWDATA(EXP_HWDATA),
.EXP_HMASTLOCK(EXP_HMASTLOCK),
- .EXP_HREADYMUX(EXP_HREADYMUX),
+ .EXP_HREADYMUX(EXP_HREADY),
// System ROM Table Region Slave Port
.SYSTABLE_HRDATA(SYSTABLE_HRDATA),
@@ -1108,7 +1111,7 @@ module nanosoc_system #(
.SYSTABLE_HPROT(SYSTABLE_HPROT),
.SYSTABLE_HWDATA(SYSTABLE_HWDATA),
.SYSTABLE_HMASTLOCK(SYSTABLE_HMASTLOCK),
- .SYSTABLE_HREADYMUX(SYSTABLE_HREADYMUX)
+ .SYSTABLE_HREADYMUX(SYSTABLE_HREADY)
);
endmodule
\ No newline at end of file
diff --git a/system/slcorem0_tech b/system/slcorem0_tech
index 40a7506..2e3ae3b 160000
--- a/system/slcorem0_tech
+++ b/system/slcorem0_tech
@@ -1 +1 @@
-Subproject commit 40a7506cd234ef65f3f7094d2e4ae9f349f5f969
+Subproject commit 2e3ae3bc669358a1ee423bb8f2af6e8e5c628966
diff --git a/testcodes/bootloader/bootrom_gen.py b/testcodes/bootloader/bootrom_gen.py
index 6a3f8d9..a053642 100755
--- a/testcodes/bootloader/bootrom_gen.py
+++ b/testcodes/bootloader/bootrom_gen.py
@@ -32,13 +32,12 @@ module bootrom (
input wire EN,
input wire [$address_width:2] ADDR,
output reg [31:0] RDATA );
-reg [$address_width:2] addr_r;
-always @(posedge CLK) if (EN) addr_r <= ADDR;
-always @(addr_r)
- case(addr_r[$address_width:2])
+always @(posedge CLK)
+if (EN)
+ case(ADDR[$address_width:2])
"""
-v_template_foot = """ default : RDATA <=32'h0;
+v_template_foot = """ default : RDATA <= 32'h0;
endcase
endmodule"""
--
GitLab