Continued Linting of NanoSoC. 800 Warnings with Temporary exclusion of SoCDebug

lint/corstone101_ip.bb

@@ -57,4 +57,16 @@ bb_list
     // Exclude SRAM Model as Arm IP
     designunit = cmsdk_fpga_sram;
     file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v;
+    
+    // Exclude APB Slave Mux as Arm IP
+    designunit = cmsdk_apb_slave_mux;
+    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v;
+    
+    // Exclude APB Test slave as Arm IP
+    designunit = cmsdk_apb_test_slave;
+    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;
+    
+    // Exclude Pads
+    designunit = PAD_INOUT8MA_NOE;
+    file = $SOCLABS_GENERIC_LIB_TECH_DIR/pads/verilog/PAD_INOUT8MA_NOE.v;
 }
\ No newline at end of file

lint/nanosoc_ip.bb

@@ -17,4 +17,8 @@ bb_list
     // Exclude Bus Matrix as Generated from Arm IP
     designunit = nanosoc_busmatrix_lite;
     file = $SOCLABS_NANOSOC_TECH_DIR/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v;
+    
+    // Temporarily Exclude SoCDebug
+    designunit = socdebug_ahb;
+    file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v;
 }
\ No newline at end of file

lint/nanosoc_ip.waive

+
+//-----------------------------------------------------------------------------
+// NanoSoC Lint Waivers 
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Wavier file for NanoSoC Chip Pads
+//-----------------------------------------------------------------------------
+lint_checking designunit = nanosoc_chip_pads
+{
+    // Combinatorial Wiring of outputs in top level of hierarchy
+    CBPAHI off;
+    
+    // Input/Output PIns decalred as inout so may have multiple drivers
+    GLTASR off;
+}
+
 lint_checking designunit = nanosoc_chip
 {
     // Combinatorial Wiring of outputs in top level of hierarchy
     CBPAHI off;
+}
+
+lint_checking designunit = bootrom
+{
+    // Combinatorial wiring through multiple levels of hierarchy to bootrom (wrappers)
+    CBPAHI off;
+}
+
+lint_checking designunit = nanosoc_clkctrl
+{
+    // Based Off of Arm IP
+    CBPAHI off;
+}
+
+lint_checking designunit = nanosoc_sysctrl
+{
+    // Based off of Arm IP
+    CBPAHI off;
+}
+
+lint_checking designunit = nanosoc_sysio_apb_ss
+{
+    // Based off of Arm IP
+    CBPAHI off;
+}
+
+lint_checking designunit = nanosoc_clkctrl
+{
+    // Reset Bypass select
+    GLTASR off;
 }
\ No newline at end of file

makefile

@@ -110,6 +110,30 @@ LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/lint
 LINT_INFO_SLCOREM0_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/lint
 LINT_INFO_SLDMA230_DIR = $(SOCLABS_SLDMA230_TECH_DIR)/lint
 
+# Capitalised Names used for Wires
+LINT_NOCHECK  = -nocheck LCVARN 
+
+# Constant values used in signal widths
+LINT_NOCHECK += -nocheck STYVAL
+
+# Maximum Length of HDL Lines exceeded (Don't care)
+LINT_NOCHECK += -nocheck MAXLEN
+
+# Outputs Assigned Asynchronously (Multiple layers of wiring)
+LINT_NOCHECK += -nocheck SYNPRT
+
+# Bitwidth not specified for Parameters
+LINT_NOCHECK += -nocheck PRMVAL
+
+# Base not specified for Parameters
+LINT_NOCHECK += -nocheck PRMBSE
+
+# Constants Used in Port Expressions (To tie them off)
+LINT_NOCHECK += -nocheck IPRTEX
+
+# TODO: Control Characters (May need to be investigated!)
+LINT_NOCHECK += -nocheck CTLCHR
+
 # MTI option
 #DF#MTI_OPTIONS    = -novopt
 MTI_OPTIONS    = -suppress 2892
@@ -199,7 +223,7 @@ compile_xm : bootrom
 lint_xm: compile_xm
 	@rm -rf $(LINT_DIR) 
 	@mkdir -p $(LINT_DIR)
-	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top nanosoc_chip $(HAL_BLACK_BOX) $(HAL_WAIVE)
+	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top nanosoc_chip_pads $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
 	
 # Note : If coverage is required, you can add -coverage all to xmelab
 

socdebug_tech @ 08356373

-Subproject commit ee1f184e8a7df3e6e461b7a331e88d0fe9be58cd
+Subproject commit 0835637304916ddcfc0c2f5a74776381e368be30