Linted Expansion Subsystem

hal/nanosoc_ip.waive

@@ -70,7 +70,26 @@ lint_checking designunit = nanosoc_ss_debug
     
     // Word Address Used only on APB
     USEPRT {"DEBUG_PADDR"} off;   
+}
+
+lint_checking designunit = nanosoc_ss_expansion
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
     
+    // FT1248 can be a one-bit bus
+    ONPNSG {"FT_"} off;
+    
+    // Word Address Used only on APB
+    USEPRT {"DEBUG_PADDR"} off;   
+}
+
+lint_checking designunit = nanosoc_region_exp
+{    
+    // In Case of Default Slave, Read Data and IRQS and DRQs constant Assigned
+    TIELOG {"HRDATA|EXP_IRQ|EXP_DRQ"} off;
+    // Some AHB Signals wont be used in this case
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT|HWRITE|EXP_DLAST"} off;
 }
 
 lint_checking designunit = nanosoc_region_bootrom_0
@@ -91,6 +110,18 @@ lint_checking designunit = nanosoc_region_dmem_0
     URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
 }
 
+lint_checking designunit = nanosoc_region_expram_l
+{   
+    // Some Bits of AHB Signals not Used
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_expram_h
+{   
+    // Some Bits of AHB Signals not Used
+    USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
 lint_checking designunit = nanosoc_bootrom_cpu_0
 {
     // Bootrom Clock name different to HCLK

system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v

@@ -65,12 +65,13 @@ module nanosoc_region_exp #(
         .HSEL         (HSEL),
         .HTRANS       (HTRANS),
         .HREADY       (HREADY),
-        .HREADYOUT    (HREADYOUTS),
-        .HRESP        (HRESPS)
+        .HREADYOUT    (HREADYOUT),
+        .HRESP        (HRESP)
     );
+    
     assign   HRDATA  = 32'heaedeaed; // Tie off Expansion Address Expansion Data
-    assign   EXP_IRQ = 4'b0;
-    assign   EXP_DRQ = 2'b0;
+    assign   EXP_IRQ = 4'd0;
+    assign   EXP_DRQ = 2'd0;
 `endif
 
 endmodule
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