Lint cleaned the cpu subsystem

flist/nanosoc_busmatrix.flist

@@ -16,8 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC BusMatrix IP search path    =============
--incdir $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
-
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v

hal/nanosoc_ip.waive

@@ -27,10 +27,62 @@ lint_checking designunit = nanosoc_chip
     CBPAHI off;
 }
 
+lint_checking designunit = nanosoc_ss_cpu
+{
+    // SYS Clock name renamed to just Clock
+    DIFCLK {"SYS_"} off;
+    
+    // Not Top-level in design_info
+    IOCOMB off;
+    TPOUNR off;
+    
+    // Some AHB Signals Unused 
+    USEPRT {"HBURST|HMASTLOCK"} off;
+}
+
+lint_checking designunit = nanosoc_region_bootrom_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_imem_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_region_dmem_0
+{   
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+}
+
+lint_checking designunit = nanosoc_bootrom_cpu_0
+{
+    // Bootrom Clock name different to HCLK
+    DIFCLK {"HCLK"} off;
+    
+    // AHB Reponse Contant for Bootrom other than rdata
+    TIELOG {"HREADYOUT|HRESP"} off;
+    
+    // Some Bits of AHB Signals not Used
+    URDPRT {"HADDR|HTRANS|HSIZE|HWDATA"} off;
+}
+
 lint_checking designunit = bootrom
 {
     // Combinatorial wiring through multiple levels of hierarchy to bootrom (wrappers)
     CBPAHI off;
+    
+    // Default Case used for simulation
+    CDEFCV off;
+    
+    // Bootrom has no Reset
+    FFWNSR off;
+    
+    // States in Case Statements needs to be more than 40
+    LMTSTS off;
 }
 
 lint_checking designunit = nanosoc_clkctrl

makefile

@@ -113,6 +113,8 @@ LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/hal
 LINT_INFO_SLCOREM0_DIR = $(SOCLABS_SLCOREM0_TECH_DIR)/hal
 LINT_INFO_SLDMA230_DIR = $(SOCLABS_SLDMA230_TECH_DIR)/hal
 
+LINT_TOP = nanosoc_chip_pads
+
 # MTI option
 #DF#MTI_OPTIONS    = -novopt
 MTI_OPTIONS    = -suppress 2892
@@ -202,7 +204,7 @@ compile_xm : bootrom
 lint_xm: bootrom
 	@rm -rf $(LINT_DIR) 
 	@mkdir -p $(LINT_DIR)
-	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top nanosoc_chip_pads $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
+	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
 	
 # Note : If coverage is required, you can add -coverage all to xmelab
 

system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v

@@ -13,7 +13,6 @@ module nanosoc_bootrom_cpu_0 #(
   parameter AW       = 10 // Address width
 )(
   input  wire          HCLK,      // Clock
-  input  wire          HRESETn,   // Reset
   input  wire          HSEL,      // Device select
   input  wire [AW-1:0] HADDR,     // Address
   input  wire    [1:0] HTRANS,    // Transfer control
@@ -25,14 +24,23 @@ module nanosoc_bootrom_cpu_0 #(
   output wire   [31:0] HRDATA,    // Read data output
   output wire          HRESP      // Device response (always OKAY)
 );
+  //------------------------
+  // Internal Wiring
+  //------------------------
+  wire   EN;
+  assign EN = HSEL & HTRANS[1] & HREADY & !HWRITE;
   
+  //------------------------
+  // Bootrom Instantiation
+  //------------------------
   bootrom u_bootrom (
     .CLK     (HCLK),
-    .EN    (HSEL & HTRANS[1] & HREADY & !HWRITE),
-    .ADDR  (HADDR[AW-1:2]),
+    .EN      (EN),
+    .W_ADDR  (HADDR[AW-1:2]),
     .RDATA   (HRDATA)
   );
   
+  // Output Signal Response Constant other than Data
   assign HREADYOUT = 1'b1;
   assign HRESP = 1'b0;
 

system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v

@@ -17,7 +17,6 @@ module nanosoc_region_bootrom_0 #(
     parameter    BOOTROM_ADDR_W = 10   // Size of Bootrom (Based on Address Width) - Default 1KB
   )(
     input  wire                   HCLK,       // Clock
-    input  wire                   HRESETn,    // Reset
 
     // AHB connection to Initiator
     input  wire                   HSEL,
@@ -38,7 +37,6 @@ module nanosoc_region_bootrom_0 #(
     .AW (BOOTROM_ADDR_W)  
   ) u_bootrom_cpu_0 (
     .HCLK             (HCLK),
-    .HRESETn          (HRESETn),
     .HSEL             (HSEL),
     .HADDR            (HADDR[9:0]),
     .HTRANS           (HTRANS),

system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v

@@ -36,8 +36,8 @@ module nanosoc_region_dmem_0 #(
 
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
+        .RAM_DATA_W (DMEM_RAM_DATA_W),
         .RAM_ADDR_W (DMEM_RAM_ADDR_W)
     ) u_dmem_0 (
         // AHB Inputs

system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v

@@ -37,9 +37,9 @@ module nanosoc_region_expram_h #(
     
     // AHB to SRAM bridge
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
-        .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W)
+        .RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W),
+        .RAM_DATA_W (EXPRAM_H_RAM_DATA_W)
     ) u_expram_h (
         // AHB Inputs
         .HCLK       (HCLK),

system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v

@@ -37,9 +37,9 @@ module nanosoc_region_expram_l #(
     
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
-        .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W)
+        .RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W),
+        .RAM_DATA_W (EXPRAM_L_RAM_DATA_W)
     ) u_expram_l (
         // AHB Inputs
         .HCLK       (HCLK),

system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v

@@ -38,9 +38,9 @@ module nanosoc_region_imem_0 #(
 
     // SRAM Instantiation
     sl_ahb_sram #(
-        .SYS_ADDR_W (SYS_ADDR_W),
         .SYS_DATA_W (SYS_DATA_W),
         .RAM_ADDR_W (IMEM_RAM_ADDR_W),
+        .RAM_DATA_W (IMEM_RAM_DATA_W),
         .FILENAME   (IMEM_RAM_FPGA_IMG)
     ) u_imem_0 (
         // AHB Inputs

system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v

@@ -85,8 +85,8 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] BOOTROM_0_HPROT,        // Protection control
     input  wire   [31:0] BOOTROM_0_HWDATA,       // Write data
     input  wire          BOOTROM_0_HMASTLOCK,    // Locked Sequence
+    input  wire          BOOTROM_0_HREADY,       // HREADY feedback
     output wire   [31:0] BOOTROM_0_HRDATA,       // Read data bus
-    output wire          BOOTROM_0_HREADY,       // HREADY feedback
     output wire          BOOTROM_0_HRESP,        // Transfer response
     output wire          BOOTROM_0_HREADYOUT,    // AHB ready out
     
@@ -100,8 +100,8 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] IMEM_0_HPROT,           // Protection control
     input  wire   [31:0] IMEM_0_HWDATA,          // Write data
     input  wire          IMEM_0_HMASTLOCK,       // Locked Sequence
+    input  wire          IMEM_0_HREADY,          // HREADY feedback
     output wire   [31:0] IMEM_0_HRDATA,          // Read data bus
-    output wire          IMEM_0_HREADY,          // HREADY feedback
     output wire          IMEM_0_HRESP,           // Transfer response
     output wire          IMEM_0_HREADYOUT,       // AHB ready out
     
@@ -115,8 +115,8 @@ module nanosoc_ss_cpu #(
     input  wire    [3:0] DMEM_0_HPROT,           // Protection control
     input  wire   [31:0] DMEM_0_HWDATA,          // Write data
     input  wire          DMEM_0_HMASTLOCK,       // Locked Sequence
+    input  wire          DMEM_0_HREADY,          // HREADY feedback
     output wire   [31:0] DMEM_0_HRDATA,          // Read data bus
-    output wire          DMEM_0_HREADY,          // HREADY feedback
     output wire          DMEM_0_HRESP,           // Transfer response
     output wire          DMEM_0_HREADYOUT,       // AHB ready out
 
@@ -213,9 +213,8 @@ module nanosoc_ss_cpu #(
         .SYS_DATA_W      (SYS_DATA_W),
         .BOOTROM_ADDR_W  (BOOTROM_ADDR_W)
     ) u_region_bootrom_0 (
-        // Clock and Reset
+        // Clock (No Reset on Bootrom)
         .HCLK(SYS_HCLK),
-        .HRESETn(SYS_HRESETn),
 
         // AHB connection to Initiator
         .HSEL(BOOTROM_0_HSEL),

testcodes/bootloader/bootrom_gen.py

@@ -30,15 +30,17 @@ v_template_head = f"""//--------------------------------------------------------
 module bootrom (
   input  wire CLK,
   input  wire EN,
-  input  wire [$address_width:2] ADDR,
+  input  wire [$word_address_width:0] W_ADDR,
   output reg [31:0] RDATA );
-always @(posedge CLK)
-if (EN)
-  case(ADDR[$address_width:2])
+always @(posedge CLK) begin
+if (EN) begin
+  case(W_ADDR)
 """
 
-v_template_foot = """    default : RDATA <= 32'h0;
+v_template_foot = """       default : RDATA <= 32'd0;
       endcase
+    end
+  end
 endmodule"""
 
 
@@ -89,6 +91,7 @@ def output_construct(input_hex, address_width):
     temp_bootrom_obj = Template(v_template_head)
     temp_verilog = temp_bootrom_obj.substitute(
         address_width=address_width+1,
+        word_address_width=address_width-1,
         date=date_str
     )
     bootrom_verilog = temp_verilog