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View file @ c9a665a3
......@@ -90,4 +90,10 @@ work
*.log*
*.cmd*
*.jou
\ No newline at end of file
*.jou
# Doc auxillary files
doc/tex/*.aux
doc/tex/*.out
doc/tex/*.toc
doc/tex/*.synctex.gz
\ No newline at end of file
doc/nanosoc_configuration_manual.pdf 0 → 100644
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File added
doc/nanosoc_datasheet.pdf 0 → 100644
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doc/tex/nanosoc_configuration_manual.tex 0 → 100644
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\documentclass{report}
\usepackage{hyperref}
\usepackage{tcolorbox,float}
\usepackage{listings}
\makeatletter
\newfloat{info@box}{tbp}{loi}[section]% 1: Name of float environment. 2: Default placement (top, bottom, ...). 3: File extension if written to an aux-file (like toc, lof, lot, loa, ...). 4: Numbering within <section/subsection/...>.
\makeatother
\floatname{info@box}{Infobox}% Adapt caption.
\newenvironment{infobox}[1][]{% Create new environment using info@box and tcolorbox
\begin{info@box}%
\begin{tcolorbox}[colback=red!15!white,% background color
colframe=red!75!black,% frame color
title=Additional information\ifstrempty{#1}{}{: #1}.% title
]%
}{%
\end{tcolorbox}%
\end{info@box}%
}
\title{nanoSoC Configuration Manual}
\author{\href{http://www.soclabs.org}{SoC Labs}}
\begin{document}
\maketitle
\input{preamble.tex}
\begin{infobox}
You must run 'source set\_env.sh' from the accelerator-project directory every time you open a new terminal!
\end{infobox} \par
\tableofcontents
\clearpage
\chapter{Introduction}
\section{Summary}
\section{Repository Structure}
The nanosoc-tech repository should be included as part of the accelerator-project repository. To use nanosoc please make sure you have cloned the accelerator-project
repository as this contains IP that nanosoc needs in order to run correctly.
You can clone the accelerator-project using the command:
\begin{lstlisting}[language=bash]
git clone --recurse-submodules \
https://git.soton.ac.uk/soclabs/accelerator-project.git
\end{lstlisting}
Below is the repository structure showing all the dependancies from the top level accelerator-project.
\begin{itemize}
\item accelerator-project (top level)
\begin{itemize}
\item \href{https://git.soton.ac.uk/soclabs/accelerator_wrapper_tech}{accelerator-wrapper-tech}
\item \href{https://git.soton.ac.uk/soclabs/asic_library_tech}{asic-lib-tech}
\item \href{https://git.soton.ac.uk/soclabs/fpga_lib_tech}{fpga-lib-tech}
\item \href{https://git.soton.ac.uk/soclabs/generic_lib_tech}{generic-lib-tech}
\item \href{https://git.soton.ac.uk/soclabs/nanosoc_tech}{nanosoc-tech}
\begin{itemize}
\item \href{https://git.soton.ac.uk/soclabs/sl_ams_tech}{sl-ams-tech}
\item \href{https://git.soton.ac.uk/soclabs/slcorem0_tech}{slcorem0-tech}
\item \href{https://git.soton.ac.uk/soclabs/sldma230_tech}{sldma230-tech}
\item \href{https://git.soton.ac.uk/soclabs/sldma350_tech}{sldm350-tech}
\item \href{https://git.soton.ac.uk/soclabs/socdebug_tech}{socdebug-tech}
\item \href{https://git.soton.ac.uk/soclabs/synopsys_28nm_slm_integration}{synopsys-28nm-slm-integration}
\end{itemize}
\item \href{https://git.soton.ac.uk/soclabs/rtl_primitives_tech}{rtl-primitives-tech}
\item \href{https://git.soton.ac.uk/soclabs/soctools_flow}{soctools-flow}
\end{itemize}
\end{itemize}
\section{IP}
The nanoSoC reusable SoC platform relies on IP's from certain vendors. In order to build the system you will need the following IP.
\subsection{Arm(R)}
Arm IP should be downloaded from Arm and placed into the recommended IP directories.
\begin{itemize}
\item Cortex-M0
\item Corstone-101
\item (Optional) PL230
\item (Optional) DMA-350
\end{itemize}
\subsection{SoCLabs}
SoCLabs IP is all open domain and the repositories for these are automatically cloned into the nanosoc tech directories when you run a git clone.
\begin{itemize}
\item ASCII Debug Protocol Controller (\href{https://git.soton.ac.uk/soclabs/socdebug_tech}{SoCDebugTech Git})
\item FT1248 Controller (\href{https://git.soton.ac.uk/soclabs/socdebug_tech}{SoCDebugTech Git})
\item EXTIO Controller (\href{https://git.soton.ac.uk/soclabs/extio8x4-axis}{ EXTIO8x4-axis Git})
\item (Optional) PLL (for TSMC 65nm)
\item (Optional) ADC (for TSMC 65nm)
\item (Optional) DAC (for TSMC 65nm)
\end{itemize}
\subsection{Synopsys} \label{synopsys_ip}
Synopsys IP is only used for chips that are taped out on a TSMC 28nm HPC+ node.
\begin{itemize}
\item (Optional) 3 GHz PLL
\item (Optional) Silicon Lifetime Management
\end{itemize}
\section{Environment Variables}\label{env_var}
\begin{infobox}
You must run 'source set\_env.sh' from the accelerator-project directory every time you open a new terminal!
\end{infobox} \par
When you run 'source set\_env.sh' it sets up environment variables that are used by the tools (simulators, fpga, synthesis etc.).
The main ones that are important for developing your IP are:
\$SOCLABS\_PROJECT\_DIR - points to the accelerator-project directory
\$ACCELERATOR\_DIR - points to your accelerator directory \\
\$ACCELERATOR\_DIR can be set up in the accelerator-project/env/dependency\_env.sh file using:
\begin{lstlisting}[language=bash]
export ACCELERATOR\_DIR="$SOCLABS\_PROJECT\_DIR/**Your-IP-directory**"
\end{lstlisting}
\chapter{Adding your IP}
In order to add the files for your IP there are 2 options. Either as a local version of your project or
as a remote version.
\begin{enumerate}
\item Local version: you can just place your IP files into a new directory or in the system/src directory
\item Remote version: you can fork the accelerator-project git to your own git account, this allows you to add your IP either in the system/src directory or as a git submodule.
\end{enumerate}
\section{Integrating your IP}
There are 2 steps to integrating your IP in nanosoc
\begin{enumerate}
\item Include your IP in the file list
\item Instantiate your IP in the system/src/accelerator\_subsystem.v file
\end{enumerate}
For step 1. you can add paths to your files in the flist/project/accelerator.flist file. We recommend that you use the environment variables as mentioned
in section \ref{env_var}. In order for fpga and asic flows to work properly you should split verilog and system verilog files into seperate .flist files.
We suggest adding an accelerator\_sv.flist to the accelerator-project/flist/project directory and adding the following to accelerator.flist \\
-f \$\(SOCLABS\_PROJECT\_DIR\)/flist/project/accelerator\_sv.flist \\
For step 2. you need to edit the accelerator\_subsystem.v file (found in accelerator-project/system/src/). The ports of this file are an AHB-lite
port, 2x EXP\_DRQ (data request from accelerator to DMA), 2x EXP\_DLAST (last signal from DMA to accelerator),
4x EXP\_IRQ (Interrupts from accelerator to CPU), and some AXI stream interfaces (these are only there if the DMA350 is configured
with stream interfaces)
\begin{infobox}
Add the option ACCELERATOR=yes to to include your accelerator when you run make commands!
\end{infobox} \par
\section{Configuring nanoSoC}
The nanoSoC reference design allows for some configuration flexibility. Most of these configuration options are in the
accelerator-project/nanosoc.config file. In order to change this configuration, put a 'yes' next to the relevant options
to include these options, otherwise leave it blank.
\subsection{DMA config}
The DMA options are fundamentally:
\begin{itemize}
\item 1x PL230
\item 2x PL230
\item 1x DMA350
\end{itemize}
More details on these DMA IP's are available from the Arm website.
The DMA-350 also has some extra configuration options
\begin{itemize}
\item DMA350\_SMALL - Small configuration of DMA, 2 channels, no stream interface, no extended features
\item DMA350\_DEFAULT - Default configuration of DMA, 2 channels, stream interface, extended features
\item DMA350\_BIG - Big configuration of DMA, 3 channels, stream interface, extended features
\end{itemize}
If you use either the SMALL or BIG options for this, you must reconfigure the DMA-350. Follow the below steps:
\begin{enumerate}
\item cd to accelerator-project/nanosoc\_tech/nanosoc/sldma350\_tech
\item run 'make clean\_ip'
\item run 'make config\_dma\_ahb\_small' or 'make config\_dma\_ahb\_big'
\end{enumerate}
\section{Mixed signal IP}
! Still under development !\\
You can also include mixed signal IP in this design. In order to do this you must also have the relevant IP for this
\section{Synopsys IP}
! Still under development !\\
If you are taping out with a TSMC 28nm node, and also have access to the Synopsys IP mentioned in section \ref{synopsys_ip}
\chapter{Simulating nanoSoC}
\section{Supported Simulators}
\begin{itemize}
\item Mentor Graphics: QuestaSim
\item Synopsys: VCS
\item Cadence: Xcelium
\item Icarus Verilog
\end{itemize}
\section{Running Simulations}
You can run make commands from the nanosoc\_tech directory to run the simulation.
\begin{lstlisting}
make run SIM=x TESTNAME=y ACCELERATOR=yes
\end{lstlisting}
Where x=mti, vcs, xm, or iverilog for QuestaSim, VCS, Xcelium, or Icarus Verilog respectively.
And y is the name of the test, the default test is hello (a hello world example).
Or to run the simulation in the GUI you can use:
\begin{lstlisting}
make sim SIM=x TESTNAME=y ACCELERATOR=yes
\end{lstlisting}
Whilst the simulation is running, you should see the output from the UART std out channel in the console/terminal.
\section{Adding Tests}
To add your own testcodes to run on nanosoc in the simulation environment, you can add these to the accelerator-project/system/testcodes directory.
\begin{enumerate}
\item Create a new directory for your testcode
\item Create a .c source file with the same name as the directory
\item Copy the makefile from one of the example testcodes to your test code directory
\item Edit the TESTNAME variable in the new makefile to the name of your test
\item If you want to run any ADP code before your test, add an adp.cmp file (example in the adp\_v4\_cmd\_tests)
\item Add the name of your test to the accelerator-project/system/software\_list.txt file
\end{enumerate}
\subsection{Creating your C code}
The below code is a basic layout for your C code. It initialises the standard out channel over UART. You can then use printf
statements that will output over UART, which will be printed on the console output.
The UartEndSimulation() function sends an escape character over UART, which the testbench will use to end the simulation.
\begin{lstlisting}[language=C, caption=Basic Template]
#include "CMSDK_CM0.h"
#include "uart_stdout.h"
#include <stdio.h>
int main(void) {
// Initialise the UART standard out channel
UartStdOutInit();
printf("Foo\n"); // Print over UART stdout
/* Insert your code here */
// End simulation by sending escape char
UartEndSimulation();
return 0;
}
\end{lstlisting}
For more detailed C code templates, please see the firmware in the
accelerator-project/nanosoc\_tech/software/common/validation.
These are also the testcodes used for validating nanoSoC.
\chapter{FPGA Flow}
\section{Summary}
\section{Building the FPGA image}
To build the FPGA image, run the below command from the nanosoc\_tech directory:
\begin{lstlisting}
make build_fpga ACCELERATOR=yes FPGA=x
\end{lstlisting}
Where x is either zcu104, mps3, kr260, kv260, z2. If you would like another FPGA target to be included
please contact the soclabs team or raise an issue on the accelerator-project git.
\section{Running test code on the FPGA}
\chapter{ASIC Flow}
\end{document}
\ No newline at end of file
doc/tex/nanosoc_datasheet.tex 0 → 100644
View file @ c9a665a3
\documentclass{report}
\usepackage{hyperref}
\title{nanoSoC Datasheet}
\author{\href{http://www.soclabs.org}{SoC Labs}}
\begin{document}
\maketitle
\input{preamble.tex}
\tableofcontents
\clearpage
\chapter{Introduction}
\section{Summary}
\chapter{System}
\section{Bus Interconnect}
\section{Address Map}
\subsection{Summary}
\begin{center}
\begin{tabular}{||c | c | c ||}
\hline
Region & Start Address & End Address \\
\hline\hline
Boot-Rom & 0x00000000 & 0x0FFFFFFF \\
\hline
Instruction Memory (SRAM) & 0x20000000 & 0x2FFFFFFF \\
\hline
Data Memory (SRAM) & 0x30000000 & 0x3FFFFFFF \\
\hline
System IO & 0x40000000 & 0x5FFFFFFF \\
\hline
Expansion IO & 0x60000000 & 0x7FFFFFFF \\
\hline
Expansion Memory Lo (SRAM) & 0x80000000 & 0x8FFFFFFF \\
\hline
Expansion Memory Hi (SRAM) & 0x90000000 & 0x9FFFFFFF \\
\hline
Expansion IO & 0xA0000000 & 0xDFFFFFFF \\
\hline
System Table ROM & 0xF0000000 & 0xF0003FFF \\
\hline
\end{tabular}
\end{center}
\subsection{System IO Region}
Below are the address regions for the System IO/Peripherals, detailed address maps for each peripheral are in chapter \ref{peripherals}
\begin{center}
\begin{tabular}{||c | c | c ||}
\hline
Region & Start Address & End Address \\
\hline\hline
Timer 0 & 0x40000000 & 0x40000FFF \\
\hline
Timer 1 & 0x40001000 & 0x40001FFF \\
\hline
Dual Timer & 0x40002000 & 0x40003FFF \\
\hline
UART 0 & 0x40004000 & 0x40004FFF \\
\hline
UART 1 & 0x40005000 & 0x40005FFF \\
\hline
UART 2 & 0x40006000 & 0x40007FFF \\
\hline
Watchdog Timer & 0x40008000 & 0x40008FFF \\
\hline
USRT 2 & 0x4000E000 & 0x4000EFFF \\
\hline
DMA 0 Base & 0x4000F000 & 0x4000EFFF \\
\hline
GPIO 0 & 0x40010000 & 0x40010FFF \\
\hline
GPIO 1 & 0x40011000 & 0x40011FFF \\
\hline
System Control & 0x4001F000 & 0x4001FFFF \\
\hline
\end{tabular}
\end{center}
\section{}
\chapter{Peripherals} \label{peripherals}
\chapter{Recommended Testboard}
\end{document}
\ No newline at end of file
doc/tex/preamble.tex 0 → 100644
View file @ c9a665a3
Preamble, copyrights licenses etc.
\ No newline at end of file
extio8x4-axis/rtl/extio8x4_axis_initiator.v
View file @ c9a665a3
......@@ -55,8 +55,12 @@ extio8x4_sync u_extio8x4_sync_ioack
.sig_s(ioack_s)
);
extio8x4_sync u_extio8x4_sync_iodata0
(
// async status on iodata4 is active-low so preset synchronizers to avoid spurious requests
extio8x4_sync # (
.RESET_VALUE(1'b1)
)
u_extio8x4_sync_iodata0 (
.clk(clk),
.resetn(resetn),
.testmode(testmode),
......@@ -64,8 +68,9 @@ extio8x4_sync u_extio8x4_sync_iodata0
.sig_s(iodata4_s[0])
);
extio8x4_sync u_extio8x4_sync_iodata1
(
extio8x4_sync # (
.RESET_VALUE(1'b1)
) u_extio8x4_sync_iodata1 (
.clk(clk),
.resetn(resetn),
.testmode(testmode),
......@@ -73,8 +78,9 @@ extio8x4_sync u_extio8x4_sync_iodata1
.sig_s(iodata4_s[1])
);
extio8x4_sync u_extio8x4_sync_iodata2
(
extio8x4_sync # (
.RESET_VALUE(1'b1)
) u_extio8x4_sync_iodata2 (
.clk(clk),
.resetn(resetn),
.testmode(testmode),
......@@ -82,8 +88,9 @@ extio8x4_sync u_extio8x4_sync_iodata2
.sig_s(iodata4_s[2])
);
extio8x4_sync u_extio8x4_sync_iodata3
(
extio8x4_sync # (
.RESET_VALUE(1'b1)
) u_extio8x4_sync_iodata3 (
.clk(clk),
.resetn(resetn),
.testmode(testmode),
......
extio8x4-axis/rtl/extio8x4_sync.v
View file @ c9a665a3
......@@ -10,8 +10,9 @@
// Copyright (c) 2024, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module extio8x4_sync
(
module extio8x4_sync #(
parameter RESET_VALUE = 1'b0
)(
input wire clk,
input wire resetn,
input wire testmode,
......@@ -24,7 +25,7 @@ reg [2:1] sig_r;
always @(posedge clk or negedge resetn)
begin
if (!resetn)
sig_r <= 2'b00; // default
sig_r <= {2{RESET_VALUE}}; // support active-low/high reset initial values
else
sig_r <= {sig_r[1], sig_a}; // shift left
end
......
fpga/makefile.targets
View file @ c9a665a3
......@@ -19,13 +19,11 @@ else ifeq ($(FPGA),zcu104)
BOARD_NAME := pynq_zcu104
PLATFORM := pynq
else ifeq ($(FPGA),kr260)
# XILINX_PART := xck26-sfvc784-2LV-c
XILINX_PART := xczu5cg-sfvc784-2LV-e
XILINX_PART := xck26-sfvc784-2LV-c
BOARD_NAME := pynq_kr260
PLATFORM := pynq
else ifeq ($(FPGA),kv260)
# XILINX_PART := xck26-sfvc784-2LV-c
XILINX_PART := xczu5cg-sfvc784-2LV-e
XILINX_PART := xck26-sfvc784-2LV-c
BOARD_NAME := pynq_kv260
PLATFORM := pynq
else ifeq ($(FPGA),z2)
......
fpga/targets/pynq_kv260/fpga_pinmap.xdc
View file @ c9a665a3
......@@ -42,20 +42,20 @@ set_property PULLUP true [get_ports {PMOD0_7}];
######################## KV260 camera ########################
# PCAM MIPI ISP
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_p}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_n}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_data_p[*]}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_data_n[*]}]
#set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_p}]
#set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_n}]
#set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_data_p[*]}]
#set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_data_n[*]}]
#I2C signals --> I2C switch 0--> ISP AP1302 + Sensor AR1335
#I2C signals --> I2C switch 1--> Sensor AR1335
#I2C signals --> I2C switch 2--> Raspi Camera
set_property PACKAGE_PIN G11 [get_ports iic_scl_io]
set_property PACKAGE_PIN F10 [get_ports iic_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports iic_*]
#set_property PACKAGE_PIN G11 [get_ports iic_scl_io]
#set_property PACKAGE_PIN F10 [get_ports iic_sda_io]
#set_property IOSTANDARD LVCMOS33 [get_ports iic_*]
# Digilent PCAM 5C MIPI Camera Enable
set_property PACKAGE_PIN F11 [get_ports "cam_gpio_tri_o[0]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L6N_HDGC_45
set_property IOSTANDARD LVCMOS33 [get_ports cam_gpio_tri_o[*]]
#set_property PACKAGE_PIN F11 [get_ports "cam_gpio_tri_o[0]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L6N_HDGC_45
#set_property IOSTANDARD LVCMOS33 [get_ports cam_gpio_tri_o[*]]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]
makefile
View file @ c9a665a3
......@@ -224,6 +224,14 @@ gen_defs:
@mkdir -p $(DEFINES_DIR)
@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
docs:
pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_datasheet.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_datasheet.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_configuration_manual.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_configuration_manual.tex
mv ./doc/tex/nanosoc_datasheet.pdf ./doc/nanosoc_datasheet.pdf
mv ./doc/tex/nanosoc_configuration_manual.pdf ./doc/nanosoc_configuration_manual.pdf
TEST_AMS:
$(info AMS is $(AMS))
$(info VCS OPTIONS is $(VCS_OPTIONS))
......
synopsys_28nm_slm_integration @ e88b3d43
Compare 5ece300b...e88b3d43
Subproject commit 5ece300bcb4e7dd8cd0c4cc141e7faa8f42e3e23
Subproject commit e88b3d4335b8416b5d78322f45e099ac9a12a1d0
projbranch
View file @ c9a665a3
......@@ -14,4 +14,5 @@ nanosoc/slcorem0_tech: main
nanosoc/sldma230_tech: main
nanosoc/socdebug_tech: main
nanosoc/sldma350_tech: main
nanosoc/sl_ams_tech: main
\ No newline at end of file
nanosoc/sl_ams_tech: main
nanosoc/synopsys_28nm_slm_integration: main
\ No newline at end of file
software/common/bootloader/bootloader.c
View file @ c9a665a3
......@@ -52,16 +52,31 @@
#include "CMSDK_CM4.h"
#endif
#define UART_CTRL_TXEN CMSDK_UART_CTRL_TXEN_Msk
#define UART_CTRL_RXEN CMSDK_UART_CTRL_RXEN_Msk
#define UART_CTRL_TXRXEN (CMSDK_UART_CTRL_TXEN_Msk + CMSDK_UART_CTRL_RXEN_Msk)
#define UART_CTRL_TXIRQEN (CMSDK_UART_CTRL_TXIRQEN_Msk + UART_CTRL_TXRXEN)
#define UART_CTRL_RXIRQEN (CMSDK_UART_CTRL_RXIRQEN_Msk + UART_CTRL_TXRXEN)
/* Global variables */
volatile int uart1_char;
void UartStdOutInit(void)
{
CMSDK_UART2->CTRL = 0x00; // re-init
CMSDK_UART2->BAUDDIV = 6250; //(240MHz/384000) in 16.4 format
CMSDK_UART2->CTRL = 0x01; //TX, UART2
CMSDK_USRT2->CTRL = 0x00; //re-init
CMSDK_USRT2->CTRL = 0x03; //RX+TX, FT1248 USRT
CMSDK_GPIO1->ALTFUNCSET = (1<<5);
if ((CMSDK_USRT2->STATE & 1)==0) CMSDK_USRT2->DATA = 0x23; // write 8'b01000011 / "#"
if ((CMSDK_UART2->STATE & 1)==0) CMSDK_UART2->DATA = 0x7e; // write 8'b01111110 / "~"
if (CMSDK_GPIO1->DATA & 0x80) {// high if FT1248
CMSDK_UART2->CTRL = 0x00; // re-init
CMSDK_UART2->BAUDDIV = 6250; //(240MHz/384000) in 16.4 format
CMSDK_UART2->CTRL = UART_CTRL_TXEN; //TX, UART2
CMSDK_GPIO1->ALTFUNCSET = (1<<5);
if ((CMSDK_UART2->STATE & 1)==0) CMSDK_UART2->DATA = 0x7e; // write 8'b01111110 / "~"
} else { // EXTIO mode - Data on UART1
CMSDK_UART1->CTRL = 0x00; //re-init
// CMSDK_UART1->CTRL = UART_CTRL_TXRXEN; //RX+TX, EXTIO
// if ((CMSDK_UART1->STATE & 1)==0) CMSDK_UART1->DATA = 0x7e; // write 8'b01111110 / "~"
}
CMSDK_USRT2->CTRL = 0x00; //re-init
CMSDK_USRT2->CTRL = UART_CTRL_TXRXEN; //RX+TX, FT1248/EXTIO USRT
if ((CMSDK_USRT2->STATE & 1)==0) CMSDK_USRT2->DATA = 0x23; // write 8'b01000011 / "#"
return;
}
......@@ -71,8 +86,8 @@ unsigned char UartPutc(unsigned char my_ch)
// while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
// CMSDK_UART2->DATA = my_ch; // write to transmit holding register
// return (my_ch);
while (((CMSDK_USRT2->STATE & 1)==1) && ((CMSDK_UART2->STATE & 1)==1)); // Wait if both Transmit Holding registers full
if ((CMSDK_USRT2->STATE & 1)==0) CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
while (((CMSDK_USRT2->STATE & 1)==1) ); // Wait if Transmit Holding register full
CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Uart string output
......@@ -134,12 +149,37 @@ void FlashLoader(void)
int main (void)
{
// UART init
// STDOUT init
UartStdOutInit();
UartPuts("\nSoCLabs NanoSoC ARM-CM0+ADP+FT1+U38400 20240110\n");
// UartPuts("\nSoCLabs NanoSoC\n");
UartPuts("\nSoCLabs NanoSoC'24 ARM-CM0+ADP+");
if (CMSDK_GPIO1->DATA & 0x80) // high if FT1248, low if EXTIO
UartPuts("FT1+U38400");
else
UartPuts("EXTIO8x4CD");
UartPuts(" 20241212\n");
/*
NVIC_EnableIRQ(UARTRX1_IRQn);
NVIC_EnableIRQ(UARTTX1_IRQn);
CMSDK_UART1->CTRL = UART_CTRL_RXIRQEN; // Enable RX interrupt
*/
FlashLoader();
return 0;
}
/*
void UARTRX1_Handler(void)
{
uart1_char = CMSDK_UART1->DATA; // read and store the byte received
CMSDK_UART1->INTCLEAR = CMSDK_UART_CTRL_RXIRQ_Msk; // Clear RX interrupt req
CMSDK_UART1->CTRL = UART_CTRL_TXIRQEN; // Enable TX interrupt
return;
}
void UARTTX1_Handler(void)
{
CMSDK_UART1->DATA = uart1_char; // write the byte to transmit
CMSDK_UART1->INTCLEAR = CMSDK_UART_CTRL_TXIRQ_Msk; // Clear TX interrupt req
CMSDK_UART1->CTRL = UART_CTRL_RXIRQEN; // Re-Enable RX interrupt
return;
}
*/
testcodes/bootloader/bootloader.hex
View file @ c9a665a3
......@@ -2,15 +2,15 @@
04
00
30
95
C9
02
00
10
9D
D1
02
00
10
9F
D3
02
00
10
......@@ -42,7 +42,7 @@
00
00
00
A1
D5
02
00
10
......@@ -54,139 +54,139 @@ A1
00
00
00
A3
D7
02
00
10
A5
D9
02
00
10
A7
DB
02
00
10
A7
DB
02
00
10
A7
DB
02
00
10
A7
DB
02
00
10
A7
DB
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A7
DB
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02
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A7
DB
02
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A7
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02
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A7
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02
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10
......@@ -250,11 +250,11 @@ AB
43
18
47
3C
70
02
00
00
5C
90
02
00
00
......@@ -324,7 +324,7 @@ B5
BD
00
F0
C5
DF
F8
11
46
......@@ -338,7 +338,7 @@ F0
F8
00
F0
DD
F7
F8
03
B4
......@@ -350,7 +350,7 @@ FF
BC
00
F0
E3
FD
F8
00
00
......@@ -366,43 +366,57 @@ F8
47
00
00
29
48
30
4A
10
68
00
22
82
60
29
49
01
61
01
21
81
60
00
06
00
28
49
8A
0D
DA
2E
48
81
60
2E
4B
03
22
8A
61
01
23
83
60
27
4B
20
22
9A
23
93
61
4A
42
68
D2
07
01
04
D1
23
7E
22
0A
02
60
01
E0
29
48
81
60
29
48
81
60
03
21
81
60
41
68
......@@ -410,65 +424,51 @@ C9
07
01
D1
7E
23
21
01
60
70
47
1D
4A
1E
24
49
4B
68
DB
07
02
D0
53
68
DB
07
F9
D1
4A
68
D2
07
00
FC
D1
08
60
70
47
30
10
B5
04
03
46
25
1C
78
00
2D
2C
02
D0
28
20
46
FF
F7
EB
F2
FF
64
5B
1C
00
2D
2C
F6
D1
30
10
BD
10
B5
14
1C
4C
20
68
......@@ -476,7 +476,7 @@ B5
28
0B
D0
13
1B
A0
FF
F7
......@@ -500,7 +500,7 @@ B8
FF
10
BD
11
19
A0
FF
F7
......@@ -510,7 +510,7 @@ FF
20
FF
F7
D0
D7
FF
FE
E7
......@@ -520,21 +520,53 @@ FF
F7
B3
FF
0F
17
A0
FF
F7
D6
FF
08
48
00
68
00
06
03
D5
1C
A0
FF
F7
CF
FF
02
E0
1D
A0
FF
F7
CB
FF
1F
A0
FF
F7
C8
FF
FF
F7
D2
FF
00
20
10
BD
00
10
01
40
00
60
00
40
......@@ -543,12 +575,12 @@ BD
00
00
00
E0
50
00
40
00
10
01
E0
00
40
00
F0
......@@ -598,6 +630,9 @@ F0
53
6F
43
27
32
34
20
41
52
......@@ -611,6 +646,10 @@ F0
44
50
2B
00
00
00
00
46
54
31
......@@ -621,19 +660,32 @@ F0
34
30
30
00
00
45
58
54
49
4F
38
78
34
43
44
00
00
20
32
30
32
34
30
31
32
31
30
32
0A
00
00
00
04
49
03
......@@ -690,7 +742,7 @@ E7
47
00
00
85
B9
02
00
10
......@@ -794,7 +846,7 @@ C0
46
FF
F7
1C
02
FF
10
BD
......@@ -822,7 +874,7 @@ E7
47
00
00
58
8C
03
00
10
......@@ -838,7 +890,7 @@ E7
01
00
10
5C
90
03
00
10
......