Initial Add datasheet tex and make target

.gitignore

@@ -90,4 +90,10 @@ work
 
 *.log*
 *.cmd*
-*.jou
\ No newline at end of file
+*.jou
+
+# Doc auxillary files
+doc/tex/*.aux
+doc/tex/*.out 
+doc/tex/*.toc
+doc/tex/*.synctex.gz
\ No newline at end of file

doc/tex/nanosoc_top.tex

+\documentclass{report}
+\usepackage{hyperref}
+
+\title{nanoSoC: Reusable microcontroller System on Chip}
+\author{\href{http://www.soclabs.org}{SoC Labs}}
+\begin{document}
+\maketitle
+Preamble, copyrights licenses etc.
+
+\tableofcontents
+\clearpage
+\chapter{Introduction}
+
+\section{Summary}
+
+\section{IP}
+The nanoSoC reusable SoC platform relies on IP's from certain vendors. In order to build the system you will need the following IP.
+\subsection{Arm(R)}
+Arm IP should be downloaded from Arm and placed into the recommended IP directories.
+\begin{itemize}
+    \item Cortex-M0
+    \item Corstone-101
+    \item (Optional) PL230
+    \item (Optional) DMA-350
+\end{itemize}
+\subsection{SoCLabs}
+SoCLabs IP is all open domain and the repositories for these are automatically cloned into the nanosoc tech directories when you run a git clone.
+\begin{itemize}
+    \item ASCII Debug Protocol Controller (\href{https://git.soton.ac.uk/soclabs/socdebug_tech}{SoCDebugTech Git})
+    \item FT1248 Controller (\href{https://git.soton.ac.uk/soclabs/socdebug_tech}{SoCDebugTech Git})
+    \item EXTIO Controller (\href{https://git.soton.ac.uk/soclabs/extio8x4-axis}{ EXTIO8x4-axis Git})
+    \item (Optional) PLL (for TSMC 65nm)
+    \item (Optional) ADC (for TSMC 65nm)
+    \item (Optional) DAC (for TSMC 65nm)
+\end{itemize}
+\subsection{Synopsys}
+Synopsys IP is only used for chips that are taped out on a TSMC 28nm HPC+ node.
+\begin{itemize}
+    \item (Optional) 3 GHz PLL
+    \item (Optional) Silicon Lifetime Management 
+\end{itemize}
+
+
+\chapter{System}
+
+\section{Bus Interconnect}
+
+\section{Address Map}
+\subsection{Summary}
+
+\begin{center}
+    \begin{tabular}{||c | c | c ||}
+        \hline
+        Region & Start Address & End Address \\ 
+        \hline\hline
+        Boot-Rom & 0x00000000 & 0x0FFFFFFF \\
+        \hline
+        Instruction Memory (SRAM) & 0x20000000 & 0x2FFFFFFF \\
+        \hline
+        Data Memory (SRAM) & 0x30000000 & 0x3FFFFFFF \\
+        \hline
+        System IO & 0x40000000 & 0x5FFFFFFF \\
+        \hline
+        Expansion IO & 0x60000000 & 0x7FFFFFFF \\
+        \hline
+        Expansion Memory Lo (SRAM) & 0x80000000 & 0x8FFFFFFF \\
+        \hline
+        Expansion Memory Hi (SRAM) & 0x90000000 & 0x9FFFFFFF \\
+        \hline
+        Expansion IO & 0xA0000000 & 0xDFFFFFFF \\
+        \hline
+        System Table ROM & 0xF0000000 & 0xF0003FFF \\
+        \hline
+    \end{tabular}
+\end{center}
+
+\subsection{System IO Region}
+Below are the address regions for the System IO/Peripherals, detailed address maps for each peripheral are in chapter \ref{peripherals}
+\begin{center}
+    \begin{tabular}{||c | c | c ||}
+        \hline
+        Region & Start Address & End Address \\ 
+        \hline\hline
+        Timer 0 & 0x40000000 & 0x40000FFF \\
+        \hline
+        Timer 1 & 0x40001000 & 0x40001FFF \\
+        \hline
+        Dual Timer & 0x40002000 & 0x40003FFF \\
+        \hline
+        UART 0 & 0x40004000 & 0x40004FFF \\
+        \hline
+        UART 1 & 0x40005000 & 0x40005FFF \\
+        \hline
+        UART 2 & 0x40006000 & 0x40007FFF \\
+        \hline
+        Watchdog Timer & 0x40008000 & 0x40008FFF \\
+        \hline
+        USRT 2  & 0x4000E000 & 0x4000EFFF \\
+        \hline
+        DMA 0 Base & 0x4000F000 & 0x4000EFFF \\
+        \hline
+        GPIO 0 & 0x40010000 & 0x40010FFF \\
+        \hline
+        GPIO 1 & 0x40011000 & 0x40011FFF \\
+        \hline
+        System Control & 0x4001F000 & 0x4001FFFF \\
+        \hline
+    \end{tabular}
+\end{center}
+
+\section{}
+
+
+\chapter{Peripherals} \label{peripherals} 
+
+\chapter{Recommended Testboard}
+
+
+\end{document}
\ No newline at end of file

makefile

@@ -224,6 +224,10 @@ gen_defs:
 	@mkdir -p $(DEFINES_DIR)
 	@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
 	
+docs:
+	pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_top.tex
+	pdflatex --output-directory=./doc/tex/ ./doc/tex/nanosoc_top.tex
+	mv ./doc/tex/nanosoc_top.pdf ./doc/nanosoc_datasheet.pdf
 TEST_AMS:
 	$(info AMS is $(AMS))
 	$(info VCS OPTIONS is $(VCS_OPTIONS))