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SoCLabs
NanoSoC Tech
Commits
d3105de7
Commit
d3105de7
authored
5 months ago
by
dwf1m12
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finally get kria kv260 FPGA target building correctly
parent
8f9cc7e7
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fpga/makefile.targets
+2
-4
2 additions, 4 deletions
fpga/makefile.targets
fpga/targets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl
+381
-26
381 additions, 26 deletions
...argets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl
with
383 additions
and
30 deletions
fpga/makefile.targets
+
2
−
4
View file @
d3105de7
...
...
@@ -19,13 +19,11 @@ else ifeq ($(FPGA),zcu104)
BOARD_NAME
:=
pynq_zcu104
PLATFORM
:=
pynq
else
ifeq
($(FPGA),kr260)
# XILINX_PART := xck26-sfvc784-2LV-c
XILINX_PART
:=
xczu5cg-sfvc784-2LV-e
XILINX_PART
:=
xck26-sfvc784-2LV-c
BOARD_NAME
:=
pynq_kr260
PLATFORM
:=
pynq
else
ifeq
($(FPGA),kv260)
# XILINX_PART := xck26-sfvc784-2LV-c
XILINX_PART
:=
xczu5cg-sfvc784-2LV-e
XILINX_PART
:=
xck26-sfvc784-2LV-c
BOARD_NAME
:=
pynq_kv260
PLATFORM
:=
pynq
else
ifeq
($(FPGA),z2)
...
...
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fpga/targets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl
+
381
−
26
View file @
d3105de7
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