IP_wrappers/PLL_integration_layer.v

@@ -58,6 +58,8 @@ reg [5:0] p_reg;
 reg [5:0] r_reg;
 reg [4:0] prediv_reg;
 
+reg pwron_reg;
+reg pll_rst;
 reg pll_lock_reg;
 
 reg [4:0] PLL_test_addr;
@@ -102,19 +104,21 @@ always @(posedge ref_clk or negedge resetn) begin
     if(~resetn) begin 
         gear_shift_counter  = 16'h0000;
         enable_counter      = 16'h0000;
+        
     end else begin 
-        if((gear_shift_reg == 1'b1)) begin
+        if((gear_shift_reg == 1'b1)&&(pll_rst==1'b1)) begin
             gear_shift_counter = gear_shift_counter+1;
             if (gear_shift_counter>16'h3E88) begin
                 gear_shift_counter = 16'h0000;
             end
-        end else begin
-            if((enp_reg==1'b0)||(enr_reg==1'b0)) begin
+        end else if(((enp_reg==1'b0)||(enr_reg==1'b0))&&(pll_rst==1'b1)) begin
                 enable_counter = enable_counter+1;
                 if(enable_counter>16'h2718) begin
                     enable_counter = 16'h0000;
                 end
-            end
+        end else begin 
+            gear_shift_counter = 16'd0;
+            enable_counter = 16'd0;
         end
     end    
 end
@@ -124,11 +128,13 @@ always @(*) begin
         bypass_reg          = 1'b0;
         enp_reg             = 1'b0; 
         enr_reg             = 1'b0;
-        gear_shift_reg      = 1'b1;
+        gear_shift_reg      = 1'b0;
         pll_lock_reg        = 1'b0;
-
+        pwron_reg           = 1'b0;
+        pll_rst             = 1'b0;
         // Default startup of PLL
         // F_vco = 100*20/1 = 1.6 GHz
+        // F_vco = F_ref * fbdiv/prediv
         // F_clkoutp = 400 MHz
         // F_clkoutr = 800 MHz
         divvcop_reg = DEFAULT_DIVVCOP; // Divvco = 1
@@ -190,15 +196,17 @@ always @(*) begin
                         enp_reg = PWDATA[4];
                         enr_reg = PWDATA[5];
                         gear_shift_reg = PWDATA[7];
-                    end else begin
-                        PSLVERR_reg = 1'b1;
+                    end  
+                    if(PSTRB[1]==1'b1) begin 
+                        pwron_reg = PWDATA[8];
+                        pll_rst = PWDATA[9];
                     end
                 end
                 10'h001: begin
-                    PSLVERR_reg = 1'b1; 
+                    PSLVERR_reg=1'b1;
                 end
                 10'h002: begin
-                    PSLVERR_reg = 1'b1; 
+                    PSLVERR_reg=1'b1;
                 end
                 10'h003: begin
                     if(PSTRB[0]==1'b1)
@@ -222,7 +230,7 @@ always @(*) begin
         end
         APB_READ: begin
             case(PADDR)
-                10'h000: PRDATA_reg = {{24{1'b0}}, gear_shift_reg, 1'b0, enr_reg, enp_reg, {3{1'b0}}, bypass_reg};
+                10'h000: PRDATA_reg = {{22{1'b0}}, pll_rst, pwron_reg, gear_shift_reg, 1'b0, enr_reg, enp_reg, {3{1'b0}}, bypass_reg};
                 10'h001: PRDATA_reg = {{20{1'b0}}, gear_shift_counter};
                 10'h002: PRDATA_reg = {{20{1'b0}}, enable_counter};
                 10'h003: PRDATA_reg = {{4{1'b0}}, divvcop_reg, {2{1'b0}}, p_reg, {4{1'b0}}, divvcor_reg, {2{1'b0}}, r_reg};
@@ -326,9 +334,9 @@ dwc_z19606ts_ns u_snps_PLL(
     .gear_shift(gear_shift_reg),  // Locking control, set high for faster PLL locking at cost of phase margin and jitter
     .p(p_reg),           // Post divider division factor P (1-64)
     .prediv(prediv_reg),      // input frequency division factor (1-32)
-    .pwron(1'b1),       // Power on control
+    .pwron(pwron_reg),       // Power on control
     .r(r_reg),           // Post divider division factor R (1-64)
-    .rst(~resetn),         // Reset signal (set high for 4us whenever PWRON goes high)
+    .rst(~pll_rst),         // Reset signal (set high for 4us whenever PWRON goes high)
 
     .vregp(),       // Output voltage regulator for P clock
     .vregr(),       // Output voltage regulator for R clock
@@ -337,7 +345,7 @@ dwc_z19606ts_ns u_snps_PLL(
     // Test Signals
     .test_data_i(PLL_data_i), //Data bus input control registers (7:0)
     .test_rd_en(PLL_test_rd_en),  // Control register read enable
-    .test_rst(~resetn),    // Control register reset signal
+    .test_rst(~pll_rst),    // Control register reset signal
     .test_sel(PLL_test_addr),    // Select lines for control register (4:0)
     .test_wr_en(PLL_test_wr_en),  // Control register write enable
     .test_data_o(PLL_data_o), //Data bus output control registers (7:0)