Doc update add initial info on sims and fpga

doc/tex/nanosoc_configuration_manual.tex

@@ -143,6 +143,11 @@ port, 2x EXP\_DRQ (data request from accelerator to DMA), 2x EXP\_DLAST (last si
 4x EXP\_IRQ (Interrupts from accelerator to CPU), and some AXI stream interfaces (these are only there if the DMA350 is configured 
 with stream interfaces)
 
+\begin{infobox}
+    Add the option ACCELERATOR=yes to to include your accelerator when you run make commands!
+\end{infobox} \par
+
+
 \section{Configuring nanoSoC}
 The nanoSoC reference design allows for some configuration flexibility. Most of these configuration options are in the 
 accelerator-project/nanosoc.config file. In order to change this configuration, put a 'yes' next to the relevant options 
@@ -187,8 +192,81 @@ If you are taping out with a TSMC 28nm node, and also have access to the Synopsy
     \item Icarus Verilog
 \end{itemize}
 
+\section{Running Simulations}
+You can run make commands from the nanosoc\_tech directory to run the simulation. 
+
+\begin{lstlisting}
+    make run SIM=x TESTNAME=y ACCELERATOR=yes
+\end{lstlisting}
+
+Where x=mti, vcs, xm, or iverilog for QuestaSim, VCS, Xcelium, or Icarus Verilog respectively.
+And y is the name of the test, the default test is hello (a hello world example).
+
+Or to run the simulation in the GUI you can use:
+
+\begin{lstlisting}
+    make sim SIM=x TESTNAME=y ACCELERATOR=yes
+\end{lstlisting}
+
+Whilst the simulation is running, you should see the output from the UART std out channel in the console/terminal.
+
+
+\section{Adding Tests}
+To add your own testcodes to run on nanosoc in the simulation environment, you can add these to the accelerator-project/system/testcodes directory.
+
+\begin{enumerate}
+    \item Create a new directory for your testcode 
+    \item Create a .c source file with the same name as the directory
+    \item Copy the makefile from one of the example testcodes to your test code directory
+    \item Edit the TESTNAME variable in the new makefile to the name of your test
+    \item If you want to run any ADP code before your test, add an adp.cmp file (example in the adp\_v4\_cmd\_tests)
+    \item Add the name of your test to the accelerator-project/system/software\_list.txt file 
+\end{enumerate}
+
+\subsection{Creating your C code}
+The below code is a basic layout for your C code. It initialises the standard out channel over UART. You can then use printf
+statements that will output over UART, which will be printed on the console output.
+
+The UartEndSimulation() function sends an escape character over UART, which the testbench will use to end the simulation.
+
+\begin{lstlisting}[language=C, caption=Basic Template]
+    #include "CMSDK_CM0.h"
+    #include "uart_stdout.h"
+    #include <stdio.h>
+    
+    int main(void) {
+        // Initialise the UART standard out channel
+        UartStdOutInit(); 
+
+        printf("Foo\n"); // Print over UART stdout
+
+        /* Insert your code here */
+
+        // End simulation by sending escape char 
+        UartEndSimulation();
+        return 0;
+    }
+\end{lstlisting}
+
+For more detailed C code templates, please see the firmware in the 
+accelerator-project/nanosoc\_tech/software/common/validation.
+These are also the testcodes used for validating nanoSoC.
+
 
 \chapter{FPGA Flow}
+\section{Summary}
+
+\section{Building the FPGA image}
+To build the FPGA image, run the below command from the nanosoc\_tech directory:
+\begin{lstlisting}
+    make build_fpga ACCELERATOR=yes FPGA=x
+\end{lstlisting}
+
+Where x is either zcu104, mps3, kr260, kv260, z2. If you would like another FPGA target to be included
+please contact the soclabs team or raise an issue on the accelerator-project git.
+
+\section{Running test code on the FPGA}
+
 
 \chapter{ASIC Flow}