core.{Data,Program}Memory: add read enable signal

src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala

@@ -11,6 +11,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   private val addrWidth = log2Ceil(cfg.dataMemoryWords)
 
   val read = IO(new Bundle {
+    val en = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
     val data = Output(UInt(512.W))
   })
@@ -26,7 +27,9 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
     else
       Mem(cfg.dataMemoryWords, UInt(512.W))
 
-  read.data := mem(read.addr)
+  when(read.en) {
+    read.data := mem(read.addr)
+  }
 
   when(write.en) {
     mem(write.addr) := write.data

src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala

@@ -20,6 +20,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   val cw = IO(Output(UInt(cwWidth.W)))
 
   val read = IO(new Bundle {
+    val en = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
     val data = Output(UInt(cwWidth.W))
   })
@@ -47,7 +48,9 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   cw := mem(pc)
 
-  read.data := mem(read.addr)
+  when(read.en) {
+    read.data := mem(read.addr)
+  }
 
   when(write.en) {
     mem(write.addr) := write.data