From 585b1228177b0ffc9c5b086d9ba71291ebd08d85 Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Sun, 11 Jul 2021 13:05:25 +0100
Subject: [PATCH] core.{Data,Program}Memory: add read enable signal
---
src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala | 5 ++++-
src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala | 5 ++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 7b89b67..0dfeb68 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -11,6 +11,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.dataMemoryWords)
val read = IO(new Bundle {
+ val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(512.W))
})
@@ -26,7 +27,9 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
else
Mem(cfg.dataMemoryWords, UInt(512.W))
- read.data := mem(read.addr)
+ when(read.en) {
+ read.data := mem(read.addr)
+ }
when(write.en) {
mem(write.addr) := write.data
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index 5d2f87e..a65cd41 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -20,6 +20,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
val cw = IO(Output(UInt(cwWidth.W)))
val read = IO(new Bundle {
+ val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(cwWidth.W))
})
@@ -47,7 +48,9 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
cw := mem(pc)
- read.data := mem(read.addr)
+ when(read.en) {
+ read.data := mem(read.addr)
+ }
when(write.en) {
mem(write.addr) := write.data
--
GitLab