diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 7b89b67c96de45bfb51c889e28b76f136ab163db..0dfeb68a94f886a38b091fccac84578e0e5595fc 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -11,6 +11,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   private val addrWidth = log2Ceil(cfg.dataMemoryWords)
 
   val read = IO(new Bundle {
+    val en = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
     val data = Output(UInt(512.W))
   })
@@ -26,7 +27,9 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
     else
       Mem(cfg.dataMemoryWords, UInt(512.W))
 
-  read.data := mem(read.addr)
+  when(read.en) {
+    read.data := mem(read.addr)
+  }
 
   when(write.en) {
     mem(write.addr) := write.data
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index 5d2f87e13fa9b68497f837a220c50516ec30cba3..a65cd41757baa91085f8f7de8df68d5438536fc2 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -20,6 +20,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   val cw = IO(Output(UInt(cwWidth.W)))
 
   val read = IO(new Bundle {
+    val en = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
     val data = Output(UInt(cwWidth.W))
   })
@@ -47,7 +48,9 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   cw := mem(pc)
 
-  read.data := mem(read.addr)
+  when(read.en) {
+    read.data := mem(read.addr)
+  }
 
   when(write.en) {
     mem(write.addr) := write.data