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Commit 40a7506c authored by dam1n19's avatar dam1n19
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Added Black Box Lint Waiver for Cortex M0 IP

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//-----------------------------------------------------------------------------
// SLCore M0 Arm Cortex M0 Lint Design Info File
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : HAL Design Info File for Blackboxing Arm IP for Cortex M0
//-----------------------------------------------------------------------------
bb_list
{
// Exclude Cortex M0 Debug Reset Synchroniser as Arm IP
designunit = cm0_dbg_reset_sync;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v;
// Exclude Cortex M0 as Arm IP
designunit = CORTEXM0;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v;
// Exclude Cortex M0 Debug Access Port as Arm IP
designunit = CORTEXM0DAP;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v;
// Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
designunit = cortexm0_wic;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
}
\ No newline at end of file
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