diff --git a/lint/cortexm0_ip.bb b/lint/cortexm0_ip.bb
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index 0000000000000000000000000000000000000000..aadce5560f5d10c417de035948f14b1adf2ad518
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+//-----------------------------------------------------------------------------
+// SLCore M0 Arm Cortex M0 Lint Design Info File
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Design Info File for Blackboxing Arm IP for Cortex M0
+//-----------------------------------------------------------------------------
+
+bb_list
+{
+    // Exclude Cortex M0 Debug Reset Synchroniser as Arm IP
+    designunit = cm0_dbg_reset_sync;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v;
+    
+    // Exclude Cortex M0 as Arm IP
+    designunit = CORTEXM0;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v;
+    
+    // Exclude Cortex M0 Debug Access Port as Arm IP
+    designunit = CORTEXM0DAP;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v;
+    
+    // Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
+    designunit = cortexm0_wic;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
+}
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