From 40a7506cd234ef65f3f7094d2e4ae9f349f5f969 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 14:35:13 +0100
Subject: [PATCH] Added Black Box Lint Waiver for Cortex M0 IP
---
lint/cortexm0_ip.bb | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 lint/cortexm0_ip.bb
diff --git a/lint/cortexm0_ip.bb b/lint/cortexm0_ip.bb
new file mode 100644
index 0000000..aadce55
--- /dev/null
+++ b/lint/cortexm0_ip.bb
@@ -0,0 +1,32 @@
+//-----------------------------------------------------------------------------
+// SLCore M0 Arm Cortex M0 Lint Design Info File
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : HAL Design Info File for Blackboxing Arm IP for Cortex M0
+//-----------------------------------------------------------------------------
+
+bb_list
+{
+ // Exclude Cortex M0 Debug Reset Synchroniser as Arm IP
+ designunit = cm0_dbg_reset_sync;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v;
+
+ // Exclude Cortex M0 as Arm IP
+ designunit = CORTEXM0;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v;
+
+ // Exclude Cortex M0 Debug Access Port as Arm IP
+ designunit = CORTEXM0DAP;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v;
+
+ // Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
+ designunit = cortexm0_wic;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
+}
\ No newline at end of file
--
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