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Commit 79e97f24 authored by dam1n19's avatar dam1n19
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STarting Refactoring FPGA flow

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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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.gitignore
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View file @ 79e97f24
......@@ -22,3 +22,6 @@ system/src/bootrom/
sim
work
*.log
*.jou
\ No newline at end of file
fpga/build_fpga.tcl 0 → 100644
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###-----------------------------------------------------------------------------
### Build FPGA Script
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
###
### David Mapstone (d.a.mapstone@soton.ac.uk)
###
### Copyright 2023, SoC Labs (www.soclabs.org)
###-----------------------------------------------------------------------------
#
# Developed & Tested using vivado_version 2021.1
#
# Get Environmnet Variables from Makefile
set fpga_name $env(FPGA_NAME)
set xilinx_part $env(FPGA_PART)
set import_dir $env(FPGA_TARGET)
set project_dir $env(FPGA_PROJECT_DIR)
set socket_lib $env(FPGA_SOCKET_LIB)
set nanosoc_lib $env(FPGA_NANOSOC_LIB)
set pynq_dir $env(FPGA_IMP_DIR)/pynq/$fpga_name/pynq/overlays/soclabs
#
# STEP#0: Build NanoSoC Design (without pads) as an "IP" library component for the testbench (in nanosoc_lib)
#
source build_nanosoc.tcl
#
# STEP#1: setup design sources and constraints
#
set_part $xilinx_part
set_property TARGET_LANGUAGE Verilog [current_project]
set_property DEFAULT_LIB work [current_project]
set paths [list \
$socket_lib\
$nanosoc_lib\
]
# Set IP repository paths
set obj [get_filesets sources_1]
if { $obj != {} } {
set_property "ip_repo_paths" "[file normalize $socket_lib] [file normalize $nanosoc_lib]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
}
report_ip_status
# #
# # STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
# #
# # using script written out from GUI capture
create_bd_design design_1
read_verilog $import_dir/design_1_wrapper.v
source $import_dir/design_1.tcl
create_root_design ""
add_files $import_dir/fpga_pinmap.xdc
set_property top design_1_wrapper [current_fileset]
# #
# # STEP#3: save in Project mode to complete flow
# #
save_project_as $fpga_name $project_dir -exclude_run_results -force
update_compile_order -fileset sources_1
# #
# # STEP#4: synthesize project
# #
set_property part $xilinx_part [get_runs synth_1]
launch_runs synth_1 -jobs 8
wait_on_run synth_1
# #
# # STEP#5: place and route project
# #
set_property part $xilinx_part [get_runs impl_1]
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
# #
# # STEP#6: export design_1.bit and design_1.hwh files for PYNQ
# #
# write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
# exec unzip -u -o $project/design_1.xsa -d $project/export
# exec mkdir -p $pynqDir
# exec cp -p $project/export/design_1.bit $pynqDir
# exec cp -p $project/export/design_1.hwh $pynqDir
# #exec rm -Rf vivado/
# exit 1
fpga/build_nanosoc.tcl 0 → 100644
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###-----------------------------------------------------------------------------
### Build NanoSoC FPGA TCL File
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
###
### David Flynn (d.w.flynn@soton.ac.uk)
###
### Copyright � 2022, SoC Labs (www.soclabs.org)
###-----------------------------------------------------------------------------
#
# developed & tested using vivado_version 2021.1
#
#
# STEP#0: setup design sources and constraints
#
source $env(FPGA_TCL_FILELIST)
set_property generic {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
set_property verilog_define {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
set_property top $env(FPGA_DESIGN_TOP) [current_fileset]
#
# STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design
#
update_compile_order -fileset sources_1
ipx::package_project -root_dir $nanosoc_lib -vendor $env(FPGA_VENDOR) -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order
ipx::unload_core $nanosoc_lib/component.xml
ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $nanosoc_lib $nanosoc_lib/component.xml
update_compile_order -fileset sources_1
set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
ipx::merge_project_changes files [ipx::current_core]
set_property core_revision $env(FPGA_CORE_REV) [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]
ipx::save_core [ipx::current_core]
ipx::check_integrity -quiet -xrt [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project
set_property ip_repo_paths " $socket_lib $nanosoc_lib" [current_project]
update_ip_catalog
close_project
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IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga
# System Design Filelist
ifeq ($(QUICKSTART),yes)
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
TB_TOP ?= nanosoc_tb_qs
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
TB_TOP ?= nanosoc_tb
endif
# Name of generated filelist by python script
TCL_FLIST_DIR := $(IMP_DIR)/flist
TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
ifeq ($(FPGA),mps3)
XILINX_PART := xcku115-flvb1760-1-c
BOARD_NAME := arm_mps3
else ifeq ($(FPGA),zcu104)
XILINX_PART := xczu7ev-ffvc1156-2-e
BOARD_NAME := pynq_zcu104
else ifeq ($(FPGA),z2)
XILINX_PART := xc7z020clg400-1
BOARD_NAME := pynq_z2
else # Default to z2
XILINX_PART := xc7z020clg400-1
BOARD_NAME := pynq_z2
endif
# Is an accelerator subsystem present in the design?
ACCELERATOR ?= yes
ifeq ($(ACCELERATOR),yes)
ACCELERATOR_SUBSYSTEM = 1
else
ACCELERATOR_SUBSYSTEM = 0
endif
FPGA_TOP ?= nanosoc_chip
# NanoSoC Synthesis Properties
VENDOR ?= soclabs.org
NANOSOC_CORE_REV ?= 2
TEMP_RTL_NANOSOC_DIR := $(IMP_DIR)/nanosoc_lib
RTL_SOCKET_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/socket/xilinx_lib
FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
RUN_DIR := $(IMP_DIR)/run
PROJECT_DIR := $(IMP_DIR)/targets/$(BOARD_NAME)
# FPGA_Flow
build_fpga: export FPGA_NAME = $(BOARD_NAME)
build_fpga: export FPGA_PART = $(XILINX_PART)
build_fpga: export FPGA_PROJECT_DIR = $(PROJECT_DIR)
build_fpga: export FPGA_TARGET = $(FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
build_fpga: export FPGA_TCL_FILELIST = $(TCL_OUTPUT_FILELIST)
build_fpga: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM)
build_fpga: export FPGA_DESIGN_TOP = $(FPGA_TOP)
build_fpga: export FPGA_VENDOR = $(VENDOR)
build_fpga: export FPGA_CORE_REV = $(NANOSOC_CORE_REV)
build_fpga: export FPGA_NANOSOC_LIB = $(TEMP_RTL_NANOSOC_DIR)
build_fpga: export FPGA_SOCKET_LIB = $(RTL_SOCKET_DIR)
build_fpga: export FPGA_IMP_DIR = $(IMP_DIR)
tcl_flist:
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(TEMP_RTL_NANOSOC_DIR);)
build_fpga: tcl_flist clean_run
@echo Starting Vivado Run
@mkdir -p $(RUN_DIR)
@cd $(RUN_DIR); vivado -mode batch -source build_fpga.tcl
clean_run:
@echo Cleaning Previous Runs of $(BOARD_NAME)
@rm -rf $(PROJECT_DIR)
@rm -rf $(TEMP_RTL_NANOSOC_DIR)
@rm -rf $(RUN_DIR)
\ No newline at end of file
fpga/targets/arm_mps3/design_1.tcl 0 → 100644
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fpga/targets/arm_mps3/design_1_wrapper.v 0 → 100644
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//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
//Date : Wed Jun 22 15:58:42 2022
//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper(
//------------------------------------------------------
// Port declarations
//------------------------------------------------------
// DDR
// output wire c0_ddr4_act_n,
// output wire [16:0] c0_ddr4_adr,
// output wire [1:0] c0_ddr4_ba,
// output wire [0:0] c0_ddr4_bg,
// output wire [0:0] c0_ddr4_cke,
// output wire [0:0] c0_ddr4_odt,
// output wire [0:0] c0_ddr4_cs_n,
// output wire [0:0] c0_ddr4_ck_t,
// output wire [0:0] c0_ddr4_ck_c,
// output wire c0_ddr4_reset_n,
// inout wire [7:0] c0_ddr4_dm_dbi_n,
// inout wire [63:0] c0_ddr4_dq,
// inout wire [7:0] c0_ddr4_dqs_t,
// inout wire [7:0] c0_ddr4_dqs_c,
// input wire c0_sys_clk_p,
// input wire c0_sys_clk_n,
// input wire DDR_nALERT,
// output wire DDR_PARITY,
// input DDR_nEVENT,
// output wire DDR_SCL,
// inout wire DDR_SDA,
// SMB
//-----------
output wire [6:0] SMBF_ADDR,
output wire SMBF_FIFOSEL,
inout wire [15:0] SMBF_DATA,
output wire SMBF_nOE,
output wire SMBF_nWE,
output wire SMBF_nRST,
output wire ETH_nCS,
output wire ETH_nOE,
input wire ETH_INT,
output wire USB_nCS,
output wire USB_DACK,
input wire USB_DREQ,
input wire USB_INT,
// HDMI
//-----------
output wire [23:0] MMB_DATA,
output wire MMB_DE,
output wire MMB_HS,
output wire MMB_VS,
output wire MMB_IDCLK,
output wire MMB_SCK,
output wire MMB_WS,
output wire [3:0] MMB_SD,
output wire HDMI_CSCL,
inout wire HDMI_CSDA,
input wire HDMI_INT,
// Audio
//-----------
output wire AUD_MCLK,
output wire AUD_SCLK,
output wire AUD_LRCK,
output wire AUD_SDIN,
input wire AUD_SDOUT,
output wire AUD_nRST,
output wire AUD_SCL,
inout wire AUD_SDA,
// EMMC
//-----------
inout wire [7:0] EMMC_DAT,
inout wire EMMC_CMD,
output wire EMMC_CLK,
output wire EMMC_nRST,
input wire EMMC_DS,
// CLCD
//-----------
inout wire [17:10] CLCD_PD,
output wire CLCD_RD,
output wire CLCD_RS,
output wire CLCD_CS,
output wire CLCD_WR_SCL,
output wire CLCD_BL,
output wire CLCD_RST,
output wire CLCD_TSCL,
inout wire CLCD_TSDA,
input wire CLCD_TINT,
output wire CLCD_TNC,
// UART
//-----------
output wire [3:0] UART_TX_F,
input wire [3:0] UART_RX_F,
// DEBUG
//-----------
input wire CS_TDI,
output wire CS_TDO, // SWV / JTAG TDO
inout wire CS_TMS, // SWD I/O / JTAG TMS
input wire CS_TCK, // SWD Clk / JTAG TCK
input wire CS_nSRST,
input wire CS_nTRST,
input wire CS_nDET,
output wire [15:0] CS_T_D, // Trace data
output wire CS_T_CLK, // Trace clock
output wire CS_T_CTL, // Trace control
// LED SW
//-----------
output wire [9:0] USER_nLED,
input wire [7:0] USER_SW,
input wire [1:0] USER_nPB,
// OSCCLK
//-----------
input wire [5:0] OSCCLK,
// FMC
//-----------
// input wire [1:0] CLK_M2C_P,
// input wire [1:0] CLK_M2C_N,
// input wire FMC_CLK_DIR,
// inout wire [3:2] CLK_BIDIR_P,
// inout wire [3:2] CLK_BIDIR_N,
// inout wire [23:0] HA_P, // HA CLK=0,1,17
// inout wire [23:0] HA_N,
// inout wire [21:0] HB_P, // HB CLK=0,6,17
// inout wire [21:0] HB_N,
// inout wire [33:0] LA_P, // LA CLK=0,1,17,18
// inout wire [33:0] LA_N,
// input wire [1:0] GBTCLK_M2C_P,
// input wire [1:0] GBTCLK_M2C_N,
// `ifdef GTH
// input wire [9:0] DP_M2C_P,
// input wire [9:0] DP_M2C_N,
// output wire [9:0] DP_C2M_P,
// output wire [9:0] DP_C2M_N,
// `endif
// input wire FMC_nPRSNT,
// input wire GTX_CLK_N,
// input wire GTX_CLK_P,
// input wire SATA_CLK_N,
// input wire SATA_CLK_P,
// Quad SPI
//-----------
inout wire QSPI_D0,
inout wire QSPI_D1,
inout wire QSPI_D2,
inout wire QSPI_D3,
output wire QSPI_SCLK,
output wire QSPI_nCS,
// USER SD
//-----------
inout wire [3:0] USD_DAT,
inout wire USD_CMD,
output wire USD_CLK,
input wire USD_NCD,
// RESET
//-----------
input wire CB_nPOR,
input wire CB_nRST,
input wire CB_RUN,
input wire IOFPGA_NRST,
input wire IOFPGA_NSPIR,
output wire IOFPGA_SYSWDT,
input wire PB_IRQ,
output wire WDOG_RREQ,
// SCC
//-----------
output wire CFG_DATAOUT,
input wire CFG_LOAD,
input wire CFG_nRST,
input wire CFG_CLK,
input wire CFG_DATAIN,
input wire CFG_WnR,
// MCC SMB
//-----------
input wire [25:16] SMBM_A,
inout wire [15:0] SMBM_D,
input wire [4:1] SMBM_nE,
input wire SMBM_CLK,
input wire [1:0] SMBM_nBL,
input wire SMBM_nOE,
input wire SMBM_nWE,
output wire SMBM_nWAIT,
// SHIELD
//-----------
inout wire [17:0] SH0_IO,
inout wire [17:0] SH1_IO,
output wire SH_nRST,
output wire SH_ADC_CS,
output wire SH_ADC_CK,
output wire SH_ADC_DI,
input wire SH_ADC_DO
// (PMOD0_0,
// PMOD0_1,
// PMOD0_2,
// PMOD0_3,
// PMOD0_4,
// PMOD0_5,
// PMOD0_6,
// PMOD0_7
);
// PMOD1_0,
// PMOD1_1,
// PMOD1_2,
// PMOD1_3,
// PMOD1_4,
// PMOD1_5,
// PMOD1_6,
// PMOD1_7,
// dip_switch_4bits_tri_i,
// led_4bits_tri_o);
wire PMOD0_0;
wire PMOD0_1;
wire PMOD0_2;
wire PMOD0_3;
wire PMOD0_4;
wire PMOD0_5;
wire PMOD0_6;
wire PMOD0_7;
// inout wire PMOD1_0;
// inout wire PMOD1_1;
// inout wire PMOD1_2;
// inout wire PMOD1_3;
// inout wire PMOD1_4;
// inout wire PMOD1_5;
// inout wire PMOD1_6;
// inout wire PMOD1_7;
// input wire [3:0]dip_switch_4bits_tri_i;
// output wire [3:0]led_4bits_tri_o;
wire [7:0]PMOD0_tri_i;
wire [7:0]PMOD0_tri_o;
wire [7:0]PMOD0_tri_z;
assign PMOD0_tri_i[0] = PMOD0_0;
assign PMOD0_tri_i[1] = PMOD0_1;
assign PMOD0_tri_i[2] = PMOD0_2;
assign PMOD0_tri_i[3] = PMOD0_3;
assign PMOD0_tri_i[4] = PMOD0_4;
assign PMOD0_tri_i[5] = PMOD0_5;
assign PMOD0_tri_i[6] = PMOD0_6;
assign PMOD0_tri_i[7] = PMOD0_7;
assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
assign SH0_IO[0] = PMOD0_0;
assign SH0_IO[1] = PMOD0_1;
assign SH0_IO[2] = PMOD0_2;
assign SH0_IO[3] = PMOD0_3;
assign CS_TMS = PMOD0_4;
assign SH0_IO[5] = PMOD0_5;
assign SH0_IO[6] = PMOD0_6;
assign CS_TCK = PMOD0_7;
// wire [7:0]PMOD1_tri_i;
// wire [7:0]PMOD1_tri_o;
// wire [7:0]PMOD1_tri_z;
// assign PMOD1_tri_i[0] = PMOD1_0;
// assign PMOD1_tri_i[1] = PMOD1_1;
// assign PMOD1_tri_i[2] = PMOD1_2;
// assign PMOD1_tri_i[3] = PMOD1_3;
// assign PMOD1_tri_i[4] = PMOD1_4;
// assign PMOD1_tri_i[5] = PMOD1_5;
// assign PMOD1_tri_i[6] = PMOD1_6;
// assign PMOD1_tri_i[7] = PMOD1_7;
// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
//REFCLK24MHZ 24 MHz
//******************************************************************************
BUFG uBUFG_REFCLK24MHZ (.I(OSCCLK[0]), .O(REFCLK24MHZ));
//ACLK Big CPU 50 MHz
//******************************************************************************
BUFG uBUFG_iACLK (.I(OSCCLK[1]), .O(ACLK)); //Big CPU 50 MHz
BUFG uBUFG_iBCLK (.I(OSCCLK[2]), .O(BCLK));
//******************************************************************************
// SMBMCLK Micro SMB 25 MHz
//******************************************************************************
BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
//******************************************************************************
// Main body of code
// =================
//******************************************************************************
assign SMBF_FIFOSEL = 1'b0;
assign SMBF_ADDR = {7{1'b0}};
assign CLCD_BL = 1'b0; // Extinguish LCD back light
// Minimum design tie-offs
assign MMB_IDCLK = 1'b0;
assign EMMC_CLK = 1'b0;
assign QSPI_nCS = 1'b1;
assign QSPI_SCLK = 1'b0;
assign IOFPGA_SYSWDT = 1'b0;
assign WDOG_RREQ = 1'b0;
assign SMBM_nWAIT = 1'b1;
assign CFG_DATAOUT = 1'b0;
wire nRST;
reg rst_sync0, rst_sync1;
assign nRST_in = CB_nRST || CS_nSRST;
always @(posedge ACLK)
if (~nRST_in) begin
rst_sync0 <= 1'b0;
rst_sync1 <= 1'b0;
end else begin
rst_sync0 <= 1'b1;
rst_sync1 <= rst_sync0;
end
assign nRST = rst_sync1;
design_1 design_1_i
(.UART_RX(UART_RX_F[2]),
.UART_TX(UART_TX_F[2]),
.EXT_CLK(ACLK),
.nRST_CPU(nRST),
.pmoda_tri_i(PMOD0_tri_i),
.pmoda_tri_o(PMOD0_tri_o),
.pmoda_tri_z(PMOD0_tri_z)
// .PMOD1_tri_i(PMOD1_tri_i),
// .PMOD1_tri_o(PMOD1_tri_o),
// .PMOD1_tri_z(PMOD1_tri_z),
// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
// .led_4bits_tri_o(led_4bits_tri_o)
);
endmodule
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synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
fpga/targets/arm_mps3/fpga_timing.xdc 0 → 100644
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##################################################################################
## ##
## Arm MPS3 Rev-C timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks SWCLK]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
fpga/targets/pynq_z2/design_1.tcl 0 → 100644
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fpga/targets/pynq_z2/design_1_wrapper.v 0 → 100644
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View file @ 79e97f24
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
//Date : Wed Jun 22 15:58:42 2022
//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(PMOD0_0,
PMOD0_1,
PMOD0_2,
PMOD0_3,
PMOD0_4,
PMOD0_5,
PMOD0_6,
PMOD0_7
);
// PMOD1_0,
// PMOD1_1,
// PMOD1_2,
// PMOD1_3,
// PMOD1_4,
// PMOD1_5,
// PMOD1_6,
// PMOD1_7,
// dip_switch_4bits_tri_i,
// led_4bits_tri_o);
inout wire PMOD0_0;
inout wire PMOD0_1;
inout wire PMOD0_2;
inout wire PMOD0_3;
inout wire PMOD0_4;
inout wire PMOD0_5;
inout wire PMOD0_6;
inout wire PMOD0_7;
// inout wire PMOD1_0;
// inout wire PMOD1_1;
// inout wire PMOD1_2;
// inout wire PMOD1_3;
// inout wire PMOD1_4;
// inout wire PMOD1_5;
// inout wire PMOD1_6;
// inout wire PMOD1_7;
// input wire [3:0]dip_switch_4bits_tri_i;
// output wire [3:0]led_4bits_tri_o;
wire [7:0]PMOD0_tri_i;
wire [7:0]PMOD0_tri_o;
wire [7:0]PMOD0_tri_z;
assign PMOD0_tri_i[0] = PMOD0_0;
assign PMOD0_tri_i[1] = PMOD0_1;
assign PMOD0_tri_i[2] = PMOD0_2;
assign PMOD0_tri_i[3] = PMOD0_3;
assign PMOD0_tri_i[4] = PMOD0_4;
assign PMOD0_tri_i[5] = PMOD0_5;
assign PMOD0_tri_i[6] = PMOD0_6;
assign PMOD0_tri_i[7] = PMOD0_7;
assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
// wire [7:0]PMOD1_tri_i;
// wire [7:0]PMOD1_tri_o;
// wire [7:0]PMOD1_tri_z;
// assign PMOD1_tri_i[0] = PMOD1_0;
// assign PMOD1_tri_i[1] = PMOD1_1;
// assign PMOD1_tri_i[2] = PMOD1_2;
// assign PMOD1_tri_i[3] = PMOD1_3;
// assign PMOD1_tri_i[4] = PMOD1_4;
// assign PMOD1_tri_i[5] = PMOD1_5;
// assign PMOD1_tri_i[6] = PMOD1_6;
// assign PMOD1_tri_i[7] = PMOD1_7;
// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
design_1 design_1_i
(.pmoda_tri_i(PMOD0_tri_i),
.pmoda_tri_o(PMOD0_tri_o),
.pmoda_tri_z(PMOD0_tri_z)//,
// .PMOD1_tri_i(PMOD1_tri_i),
// .PMOD1_tri_o(PMOD1_tri_o),
// .PMOD1_tri_z(PMOD1_tri_z),
// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
// .led_4bits_tri_o(led_4bits_tri_o)
);
endmodule
fpga/targets/pynq_z2/fpga_pinmap.xdc 0 → 100644
+ 33
− 0
View file @ 79e97f24
##################################################################################
## ##
## PZ2 PMODA XDC ##
## ##
##################################################################################
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
set_property PULLUP true [get_ports PMOD0_2]
set_property PULLDOWN true [get_ports PMOD0_3]
set_property PULLUP true [get_ports PMOD0_4]
set_property PULLUP true [get_ports PMOD0_5]
set_property PULLUP true [get_ports PMOD0_6]
set_property PULLUP true [get_ports PMOD0_7]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
fpga/targets/pynq_z2/fpga_synth.tcl 0 → 100644
+ 1
− 0
View file @ 79e97f24
synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
fpga/targets/pynq_z2/fpga_timing.xdc 0 → 100644
+ 95
− 0
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##################################################################################
## ##
## ZYNQ timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks VSWCLK]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
#connect_debug_port dbg_hub/clk [get_nets clk]
fpga/targets/pynq_zcu104/design_1.tcl 0 → 100644
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fpga/targets/pynq_zcu104/design_1_wrapper.v 0 → 100644
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//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
//Date : Wed Jun 22 15:58:42 2022
//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(PMOD0_0,
PMOD0_1,
PMOD0_2,
PMOD0_3,
PMOD0_4,
PMOD0_5,
PMOD0_6,
PMOD0_7
);
// PMOD1_0,
// PMOD1_1,
// PMOD1_2,
// PMOD1_3,
// PMOD1_4,
// PMOD1_5,
// PMOD1_6,
// PMOD1_7,
// dip_switch_4bits_tri_i,
// led_4bits_tri_o);
inout wire PMOD0_0;
inout wire PMOD0_1;
inout wire PMOD0_2;
inout wire PMOD0_3;
inout wire PMOD0_4;
inout wire PMOD0_5;
inout wire PMOD0_6;
inout wire PMOD0_7;
// inout wire PMOD1_0;
// inout wire PMOD1_1;
// inout wire PMOD1_2;
// inout wire PMOD1_3;
// inout wire PMOD1_4;
// inout wire PMOD1_5;
// inout wire PMOD1_6;
// inout wire PMOD1_7;
// input wire [3:0]dip_switch_4bits_tri_i;
// output wire [3:0]led_4bits_tri_o;
wire [7:0]PMOD0_tri_i;
wire [7:0]PMOD0_tri_o;
wire [7:0]PMOD0_tri_z;
assign PMOD0_tri_i[0] = PMOD0_0;
assign PMOD0_tri_i[1] = PMOD0_1;
assign PMOD0_tri_i[2] = PMOD0_2;
assign PMOD0_tri_i[3] = PMOD0_3;
assign PMOD0_tri_i[4] = PMOD0_4;
assign PMOD0_tri_i[5] = PMOD0_5;
assign PMOD0_tri_i[6] = PMOD0_6;
assign PMOD0_tri_i[7] = PMOD0_7;
assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
// wire [7:0]PMOD1_tri_i;
// wire [7:0]PMOD1_tri_o;
// wire [7:0]PMOD1_tri_z;
// assign PMOD1_tri_i[0] = PMOD1_0;
// assign PMOD1_tri_i[1] = PMOD1_1;
// assign PMOD1_tri_i[2] = PMOD1_2;
// assign PMOD1_tri_i[3] = PMOD1_3;
// assign PMOD1_tri_i[4] = PMOD1_4;
// assign PMOD1_tri_i[5] = PMOD1_5;
// assign PMOD1_tri_i[6] = PMOD1_6;
// assign PMOD1_tri_i[7] = PMOD1_7;
// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
design_1 design_1_i
(.pmoda_tri_i(PMOD0_tri_i),
.pmoda_tri_o(PMOD0_tri_o),
.pmoda_tri_z(PMOD0_tri_z)//,
// .PMOD1_tri_i(PMOD1_tri_i),
// .PMOD1_tri_o(PMOD1_tri_o),
// .PMOD1_tri_z(PMOD1_tri_z),
// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
// .led_4bits_tri_o(led_4bits_tri_o)
);
endmodule
fpga/targets/pynq_zcu104/fpga_pinmap.xdc 0 → 100644
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fpga/targets/pynq_zcu104/fpga_synth.tcl 0 → 100644
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synth_design -top nanosoc_chip -part xczu7ev-ffvc1156-2-e
fpga/targets/pynq_zcu104/fpga_timing.xdc 0 → 100644
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##################################################################################
## ##
## ZYNQ timing XDC ##
## ##
##################################################################################
create_clock -name CLK -period 30 [get_ports xtal_clk_i]
create_clock -name VCLK -period 30 -waveform {5 20}
create_clock -name SWCLK -period 60 [get_ports swdclk_i]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks VSWCLK]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[15]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[0]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[0]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[1]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[1]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[2]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[2]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[3]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[3]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[4]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[4]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[5]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[5]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[6]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[6]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[7]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[7]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[8]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[8]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[9]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[9]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[10]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[10]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[11]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[11]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[12]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[12]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[13]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[13]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[14]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[14]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[15]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[15]}]
#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
#connect_debug_port dbg_hub/clk [get_nets clk]
fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
+ 1
− 3
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......@@ -28,7 +28,6 @@ set pynqDir pynq_export/pz104/pynq/overlays/soclabs
# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
#
source scripts/build_mcu_fpga_ip.tcl
set_property include_dirs " $env(ACCELERATOR_DIR)/src/rtl $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines/ $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines" [current_fileset]
#
# STEP#1: setup design sources and constraints
#
......@@ -82,8 +81,7 @@ set_property top design_1_wrapper [current_fileset]
#
# STEP#3: save in Project mode to complete flow
#
save_project_as $project ./$project -exclude_run_results -force -scan_for_includes
save_project_as $project ./$project -exclude_run_results -force
update_compile_order -fileset sources_1
......
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