diff --git a/.gitignore b/.gitignore
index 4f177e8813809f4625e5bf3d3be8873362e81052..aed68fee3e230f5821eda7a011ebc67ce3c1a549 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,4 +21,7 @@ system/src/bootrom/
# Simulation Removal (If running at Tech Level)
sim
-work
\ No newline at end of file
+work
+
+*.log
+*.jou
\ No newline at end of file
diff --git a/fpga/build_fpga.tcl b/fpga/build_fpga.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..314dd2abcf8644af5a74c06a44ae10aeaf37f433
--- /dev/null
+++ b/fpga/build_fpga.tcl
@@ -0,0 +1,104 @@
+###-----------------------------------------------------------------------------
+### Build FPGA Script
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Mapstone (d.a.mapstone@soton.ac.uk)
+###
+### Copyright 2023, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# Developed & Tested using vivado_version 2021.1
+#
+
+# Get Environmnet Variables from Makefile
+set fpga_name $env(FPGA_NAME)
+set xilinx_part $env(FPGA_PART)
+set import_dir $env(FPGA_TARGET)
+set project_dir $env(FPGA_PROJECT_DIR)
+
+set socket_lib $env(FPGA_SOCKET_LIB)
+set nanosoc_lib $env(FPGA_NANOSOC_LIB)
+set pynq_dir $env(FPGA_IMP_DIR)/pynq/$fpga_name/pynq/overlays/soclabs
+
+#
+# STEP#0: Build NanoSoC Design (without pads) as an "IP" library component for the testbench (in nanosoc_lib)
+#
+source build_nanosoc.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $socket_lib\
+ $nanosoc_lib\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $socket_lib] [file normalize $nanosoc_lib]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+# #
+# # STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+# #
+# # using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $import_dir/design_1_wrapper.v
+source $import_dir/design_1.tcl
+create_root_design ""
+
+
+add_files $import_dir/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+# #
+# # STEP#3: save in Project mode to complete flow
+# #
+save_project_as $fpga_name $project_dir -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+# #
+# # STEP#4: synthesize project
+# #
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+# #
+# # STEP#5: place and route project
+# #
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+# #
+# # STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+# #
+
+# write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+# exec unzip -u -o $project/design_1.xsa -d $project/export
+# exec mkdir -p $pynqDir
+# exec cp -p $project/export/design_1.bit $pynqDir
+# exec cp -p $project/export/design_1.hwh $pynqDir
+
+# #exec rm -Rf vivado/
+
+# exit 1
diff --git a/fpga/build_nanosoc.tcl b/fpga/build_nanosoc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e38f6b4ad0460c57a8e2dd883e71e0956f5f2c07
--- /dev/null
+++ b/fpga/build_nanosoc.tcl
@@ -0,0 +1,54 @@
+###-----------------------------------------------------------------------------
+### Build NanoSoC FPGA TCL File
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright � 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+
+
+#
+# STEP#0: setup design sources and constraints
+#
+source $env(FPGA_TCL_FILELIST)
+
+
+set_property generic {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
+set_property verilog_define {ACCELERATOR_SUBSYSTEM=$env(FPGA_ACCELERATOR_SUBSYSTEM)} [current_fileset]
+set_property top $env(FPGA_DESIGN_TOP) [current_fileset]
+
+#
+# STEP#1: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+
+update_compile_order -fileset sources_1
+
+ipx::package_project -root_dir $nanosoc_lib -vendor $env(FPGA_VENDOR) -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order
+
+ipx::unload_core $nanosoc_lib/component.xml
+ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $nanosoc_lib $nanosoc_lib/component.xml
+
+update_compile_order -fileset sources_1
+set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
+ipx::merge_project_changes files [ipx::current_core]
+
+set_property core_revision $env(FPGA_CORE_REV) [ipx::current_core]
+ipx::update_source_project_archive -component [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::check_integrity [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+ipx::check_integrity -quiet -xrt [ipx::current_core]
+ipx::move_temp_component_back -component [ipx::current_core]
+close_project
+
+set_property ip_repo_paths " $socket_lib $nanosoc_lib" [current_project]
+update_ip_catalog
+close_project
diff --git a/fpga/makefile b/fpga/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..812ae557897f62fb2c95604351c1a72f9a63debe
--- /dev/null
+++ b/fpga/makefile
@@ -0,0 +1,87 @@
+IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga
+
+# System Design Filelist
+ifeq ($(QUICKSTART),yes)
+ DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
+ TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
+ ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical
+ ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
+ TB_TOP ?= nanosoc_tb_qs
+else
+ DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+ TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+ ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+ ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+ TB_TOP ?= nanosoc_tb
+endif
+
+# Name of generated filelist by python script
+TCL_FLIST_DIR := $(IMP_DIR)/flist
+TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
+
+ifeq ($(FPGA),mps3)
+ XILINX_PART := xcku115-flvb1760-1-c
+ BOARD_NAME := arm_mps3
+else ifeq ($(FPGA),zcu104)
+ XILINX_PART := xczu7ev-ffvc1156-2-e
+ BOARD_NAME := pynq_zcu104
+else ifeq ($(FPGA),z2)
+ XILINX_PART := xc7z020clg400-1
+ BOARD_NAME := pynq_z2
+else # Default to z2
+ XILINX_PART := xc7z020clg400-1
+ BOARD_NAME := pynq_z2
+endif
+
+# Is an accelerator subsystem present in the design?
+ACCELERATOR ?= yes
+
+ifeq ($(ACCELERATOR),yes)
+ ACCELERATOR_SUBSYSTEM = 1
+else
+ ACCELERATOR_SUBSYSTEM = 0
+endif
+
+FPGA_TOP ?= nanosoc_chip
+
+# NanoSoC Synthesis Properties
+VENDOR ?= soclabs.org
+NANOSOC_CORE_REV ?= 2
+
+TEMP_RTL_NANOSOC_DIR := $(IMP_DIR)/nanosoc_lib
+RTL_SOCKET_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/socket/xilinx_lib
+
+FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
+
+RUN_DIR := $(IMP_DIR)/run
+PROJECT_DIR := $(IMP_DIR)/targets/$(BOARD_NAME)
+
+# FPGA_Flow
+build_fpga: export FPGA_NAME = $(BOARD_NAME)
+build_fpga: export FPGA_PART = $(XILINX_PART)
+build_fpga: export FPGA_PROJECT_DIR = $(PROJECT_DIR)
+build_fpga: export FPGA_TARGET = $(FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
+build_fpga: export FPGA_TCL_FILELIST = $(TCL_OUTPUT_FILELIST)
+build_fpga: export FPGA_ACCELERATOR = $(ACCELERATOR_SUBSYSTEM)
+build_fpga: export FPGA_DESIGN_TOP = $(FPGA_TOP)
+build_fpga: export FPGA_VENDOR = $(VENDOR)
+build_fpga: export FPGA_CORE_REV = $(NANOSOC_CORE_REV)
+build_fpga: export FPGA_NANOSOC_LIB = $(TEMP_RTL_NANOSOC_DIR)
+build_fpga: export FPGA_SOCKET_LIB = $(RTL_SOCKET_DIR)
+build_fpga: export FPGA_IMP_DIR = $(IMP_DIR)
+
+tcl_flist:
+ @mkdir -p $(TCL_FLIST_DIR)
+ @(cd $(TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(TEMP_RTL_NANOSOC_DIR);)
+
+build_fpga: tcl_flist clean_run
+ @echo Starting Vivado Run
+ @mkdir -p $(RUN_DIR)
+ @cd $(RUN_DIR); vivado -mode batch -source build_fpga.tcl
+
+clean_run:
+ @echo Cleaning Previous Runs of $(BOARD_NAME)
+ @rm -rf $(PROJECT_DIR)
+ @rm -rf $(TEMP_RTL_NANOSOC_DIR)
+ @rm -rf $(RUN_DIR)
\ No newline at end of file
diff --git a/fpga/targets/arm_mps3/design_1.tcl b/fpga/targets/arm_mps3/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..becad422ab87900f409f7faa2e79a82e938da8da
--- /dev/null
+++ b/fpga/targets/arm_mps3/design_1.tcl
@@ -0,0 +1,606 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xcku115-flvb1760-1-c
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+
+ # Create pins
+ create_bd_pin -dir I UART_RX
+ create_bd_pin -dir O UART_TX
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.ADVANCED_PROPERTIES {0} \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: uart_to_AXI_master_0, and set properties
+ set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_to_AXI_master:1.0 uart_to_AXI_master_0 ]
+ set_property -dict [ list \
+ CONFIG.CLK_SPEED {50000000} \
+ CONFIG.C_M00_AXI_ARUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_AWUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_BUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_ID_WIDTH {4} \
+ CONFIG.C_M00_AXI_RUSER_WIDTH {4} \
+ CONFIG.C_M00_AXI_WUSER_WIDTH {4} \
+ ] $uart_to_AXI_master_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net uart_to_AXI_master_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net UART_RX_1 [get_bd_pins UART_RX] [get_bd_pins uart_to_AXI_master_0/UART_RX]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_stream_io_0_tx_tdata [get_bd_pins axi_stream_io_0/tx_tdata] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tdata8_i]
+ connect_bd_net -net axi_stream_io_0_tx_tvalid [get_bd_pins axi_stream_io_0/tx_tvalid] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tvalid_i]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ft1248x1_to_axi_stream_0_rxd_tready_o [get_bd_pins axi_stream_io_0/tx_tready] [get_bd_pins ft1248x1_to_axi_stream_0/rxd_tready_o]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ext_reset_in] [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins uart_to_AXI_master_0/m00_axi_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net uart_to_AXI_master_0_UART_TX [get_bd_pins UART_TX] [get_bd_pins uart_to_AXI_master_0/UART_TX]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins uart_to_AXI_master_0/m00_axi_aclk]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set EXT_CLK [ create_bd_port -dir I -type clk -freq_hz 50000000 EXT_CLK ]
+ # set_property -dict [ list \
+ # CONFIG.ASSOCIATED_ASYNC_RESET {nRST_CPU} \
+ # CONFIG.ASSOCIATED_RESET {nRST_CPU} \
+ #] $EXT_CLK
+ set UART_RX [ create_bd_port -dir I UART_RX ]
+ set UART_TX [ create_bd_port -dir O UART_TX ]
+ set nRST_CPU [ create_bd_port -dir I -type rst nRST_CPU ]
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create port connections
+ connect_bd_net -net EXT_CLK_1 [get_bd_ports EXT_CLK] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i]
+ connect_bd_net -net UART_RX_1 [get_bd_ports UART_RX] [get_bd_pins cmsdk_socket/UART_RX]
+ connect_bd_net -net cmsdk_socket_UART_TX [get_bd_ports UART_TX] [get_bd_pins cmsdk_socket/UART_TX]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net rst_sync_0_reset [get_bd_ports nRST_CPU] [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+
+ # Create address segments
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cmsdk_socket/uart_to_AXI_master_0/M00_AXI] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+#create_root_design ""
+
+
diff --git a/fpga/targets/arm_mps3/design_1_wrapper.v b/fpga/targets/arm_mps3/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..01c9af767cb75aa8f62f5a3cb9aeadb4d967b98e
--- /dev/null
+++ b/fpga/targets/arm_mps3/design_1_wrapper.v
@@ -0,0 +1,384 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper(
+//------------------------------------------------------
+// Port declarations
+//------------------------------------------------------
+
+// DDR
+ // output wire c0_ddr4_act_n,
+ // output wire [16:0] c0_ddr4_adr,
+ // output wire [1:0] c0_ddr4_ba,
+ // output wire [0:0] c0_ddr4_bg,
+ // output wire [0:0] c0_ddr4_cke,
+ // output wire [0:0] c0_ddr4_odt,
+ // output wire [0:0] c0_ddr4_cs_n,
+ // output wire [0:0] c0_ddr4_ck_t,
+ // output wire [0:0] c0_ddr4_ck_c,
+ // output wire c0_ddr4_reset_n,
+ // inout wire [7:0] c0_ddr4_dm_dbi_n,
+ // inout wire [63:0] c0_ddr4_dq,
+ // inout wire [7:0] c0_ddr4_dqs_t,
+ // inout wire [7:0] c0_ddr4_dqs_c,
+ // input wire c0_sys_clk_p,
+ // input wire c0_sys_clk_n,
+ // input wire DDR_nALERT,
+ // output wire DDR_PARITY,
+ // input DDR_nEVENT,
+ // output wire DDR_SCL,
+ // inout wire DDR_SDA,
+
+// SMB
+//-----------
+ output wire [6:0] SMBF_ADDR,
+ output wire SMBF_FIFOSEL,
+ inout wire [15:0] SMBF_DATA,
+ output wire SMBF_nOE,
+ output wire SMBF_nWE,
+ output wire SMBF_nRST,
+
+ output wire ETH_nCS,
+ output wire ETH_nOE,
+ input wire ETH_INT,
+
+ output wire USB_nCS,
+ output wire USB_DACK,
+ input wire USB_DREQ,
+ input wire USB_INT,
+
+// HDMI
+//-----------
+ output wire [23:0] MMB_DATA,
+ output wire MMB_DE,
+ output wire MMB_HS,
+ output wire MMB_VS,
+ output wire MMB_IDCLK,
+ output wire MMB_SCK,
+ output wire MMB_WS,
+ output wire [3:0] MMB_SD,
+
+ output wire HDMI_CSCL,
+ inout wire HDMI_CSDA,
+ input wire HDMI_INT,
+
+// Audio
+//-----------
+ output wire AUD_MCLK,
+ output wire AUD_SCLK,
+ output wire AUD_LRCK,
+ output wire AUD_SDIN,
+ input wire AUD_SDOUT,
+
+ output wire AUD_nRST,
+ output wire AUD_SCL,
+ inout wire AUD_SDA,
+
+// EMMC
+//-----------
+ inout wire [7:0] EMMC_DAT,
+ inout wire EMMC_CMD,
+ output wire EMMC_CLK,
+ output wire EMMC_nRST,
+ input wire EMMC_DS,
+
+// CLCD
+//-----------
+ inout wire [17:10] CLCD_PD,
+ output wire CLCD_RD,
+ output wire CLCD_RS,
+ output wire CLCD_CS,
+ output wire CLCD_WR_SCL,
+ output wire CLCD_BL,
+ output wire CLCD_RST,
+
+ output wire CLCD_TSCL,
+ inout wire CLCD_TSDA,
+ input wire CLCD_TINT,
+ output wire CLCD_TNC,
+
+// UART
+//-----------
+ output wire [3:0] UART_TX_F,
+
+ input wire [3:0] UART_RX_F,
+
+// DEBUG
+//-----------
+ input wire CS_TDI,
+ output wire CS_TDO, // SWV / JTAG TDO
+ inout wire CS_TMS, // SWD I/O / JTAG TMS
+ input wire CS_TCK, // SWD Clk / JTAG TCK
+ input wire CS_nSRST,
+ input wire CS_nTRST,
+ input wire CS_nDET,
+
+ output wire [15:0] CS_T_D, // Trace data
+ output wire CS_T_CLK, // Trace clock
+ output wire CS_T_CTL, // Trace control
+
+// LED SW
+//-----------
+ output wire [9:0] USER_nLED,
+ input wire [7:0] USER_SW,
+ input wire [1:0] USER_nPB,
+
+// OSCCLK
+//-----------
+ input wire [5:0] OSCCLK,
+
+// FMC
+//-----------
+ // input wire [1:0] CLK_M2C_P,
+ // input wire [1:0] CLK_M2C_N,
+
+ // input wire FMC_CLK_DIR,
+
+ // inout wire [3:2] CLK_BIDIR_P,
+ // inout wire [3:2] CLK_BIDIR_N,
+
+ // inout wire [23:0] HA_P, // HA CLK=0,1,17
+ // inout wire [23:0] HA_N,
+
+ // inout wire [21:0] HB_P, // HB CLK=0,6,17
+ // inout wire [21:0] HB_N,
+
+ // inout wire [33:0] LA_P, // LA CLK=0,1,17,18
+ // inout wire [33:0] LA_N,
+
+ // input wire [1:0] GBTCLK_M2C_P,
+ // input wire [1:0] GBTCLK_M2C_N,
+// `ifdef GTH
+ // input wire [9:0] DP_M2C_P,
+ // input wire [9:0] DP_M2C_N,
+
+ // output wire [9:0] DP_C2M_P,
+ // output wire [9:0] DP_C2M_N,
+// `endif
+ // input wire FMC_nPRSNT,
+
+ // input wire GTX_CLK_N,
+ // input wire GTX_CLK_P,
+
+ // input wire SATA_CLK_N,
+ // input wire SATA_CLK_P,
+
+// Quad SPI
+//-----------
+ inout wire QSPI_D0,
+ inout wire QSPI_D1,
+ inout wire QSPI_D2,
+ inout wire QSPI_D3,
+ output wire QSPI_SCLK,
+ output wire QSPI_nCS,
+
+// USER SD
+//-----------
+ inout wire [3:0] USD_DAT,
+ inout wire USD_CMD,
+ output wire USD_CLK,
+ input wire USD_NCD,
+
+// RESET
+//-----------
+ input wire CB_nPOR,
+ input wire CB_nRST,
+ input wire CB_RUN,
+
+ input wire IOFPGA_NRST,
+ input wire IOFPGA_NSPIR,
+
+ output wire IOFPGA_SYSWDT,
+ input wire PB_IRQ,
+ output wire WDOG_RREQ,
+
+// SCC
+//-----------
+ output wire CFG_DATAOUT,
+ input wire CFG_LOAD,
+ input wire CFG_nRST,
+ input wire CFG_CLK,
+ input wire CFG_DATAIN,
+ input wire CFG_WnR,
+
+// MCC SMB
+//-----------
+ input wire [25:16] SMBM_A,
+ inout wire [15:0] SMBM_D,
+ input wire [4:1] SMBM_nE,
+ input wire SMBM_CLK,
+ input wire [1:0] SMBM_nBL,
+ input wire SMBM_nOE,
+ input wire SMBM_nWE,
+ output wire SMBM_nWAIT,
+
+// SHIELD
+//-----------
+ inout wire [17:0] SH0_IO,
+ inout wire [17:0] SH1_IO,
+ output wire SH_nRST,
+
+ output wire SH_ADC_CS,
+ output wire SH_ADC_CK,
+ output wire SH_ADC_DI,
+ input wire SH_ADC_DO
+// (PMOD0_0,
+// PMOD0_1,
+// PMOD0_2,
+// PMOD0_3,
+// PMOD0_4,
+// PMOD0_5,
+// PMOD0_6,
+// PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ wire PMOD0_0;
+ wire PMOD0_1;
+ wire PMOD0_2;
+ wire PMOD0_3;
+ wire PMOD0_4;
+ wire PMOD0_5;
+ wire PMOD0_6;
+ wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+ assign SH0_IO[0] = PMOD0_0;
+ assign SH0_IO[1] = PMOD0_1;
+ assign SH0_IO[2] = PMOD0_2;
+ assign SH0_IO[3] = PMOD0_3;
+ assign CS_TMS = PMOD0_4;
+ assign SH0_IO[5] = PMOD0_5;
+ assign SH0_IO[6] = PMOD0_6;
+ assign CS_TCK = PMOD0_7;
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+//REFCLK24MHZ 24 MHz
+//******************************************************************************
+BUFG uBUFG_REFCLK24MHZ (.I(OSCCLK[0]), .O(REFCLK24MHZ));
+
+//ACLK Big CPU 50 MHz
+//******************************************************************************
+BUFG uBUFG_iACLK (.I(OSCCLK[1]), .O(ACLK)); //Big CPU 50 MHz
+BUFG uBUFG_iBCLK (.I(OSCCLK[2]), .O(BCLK));
+//******************************************************************************
+// SMBMCLK Micro SMB 25 MHz
+//******************************************************************************
+BUFG uBUFG_SMBM (.I(SMBM_CLK), .O(iSMBMCLK)); //Micro SMB
+
+//******************************************************************************
+// Main body of code
+// =================
+//******************************************************************************
+ assign SMBF_FIFOSEL = 1'b0;
+ assign SMBF_ADDR = {7{1'b0}};
+ assign CLCD_BL = 1'b0; // Extinguish LCD back light
+ // Minimum design tie-offs
+ assign MMB_IDCLK = 1'b0;
+ assign EMMC_CLK = 1'b0;
+ assign QSPI_nCS = 1'b1;
+ assign QSPI_SCLK = 1'b0;
+ assign IOFPGA_SYSWDT = 1'b0;
+ assign WDOG_RREQ = 1'b0;
+ assign SMBM_nWAIT = 1'b1;
+ assign CFG_DATAOUT = 1'b0;
+ wire nRST;
+ reg rst_sync0, rst_sync1;
+ assign nRST_in = CB_nRST || CS_nSRST;
+
+ always @(posedge ACLK)
+ if (~nRST_in) begin
+ rst_sync0 <= 1'b0;
+ rst_sync1 <= 1'b0;
+ end else begin
+ rst_sync0 <= 1'b1;
+ rst_sync1 <= rst_sync0;
+ end
+
+ assign nRST = rst_sync1;
+
+
+ design_1 design_1_i
+ (.UART_RX(UART_RX_F[2]),
+ .UART_TX(UART_TX_F[2]),
+ .EXT_CLK(ACLK),
+ .nRST_CPU(nRST),
+ .pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/fpga/targets/arm_mps3/fpga_pinmap.xdc b/fpga/targets/arm_mps3/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5fbe61eb28f3d716824d54418909d555a4f29ad4
--- /dev/null
+++ b/fpga/targets/arm_mps3/fpga_pinmap.xdc
@@ -0,0 +1,915 @@
+# -----------------------------------------------------------------------------
+# Purpose : Main timing constraints and pin list for MPS3
+# -----------------------------------------------------------------------------
+
+####################################################################################
+# Pin Assigment
+####################################################################################
+
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_* ETH_* USB_* CLCD_* USER_nLED* USER_SW* USER_nPB* HDMI_* CS_* SH_ADC* UART_*}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[23]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[22]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[21]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[20]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[18]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_DE]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_HS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_IDCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_VS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_WS]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CMD]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_DS]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_nRST]
+# not used
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[2]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[2]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_LRCK]
+set_property PACKAGE_PIN Y30 [get_ports AUD_LRCK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_MCLK]
+set_property PACKAGE_PIN AB29 [get_ports AUD_MCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_nRST]
+set_property PACKAGE_PIN AA27 [get_ports AUD_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCL]
+set_property PACKAGE_PIN AA28 [get_ports AUD_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCLK]
+set_property PACKAGE_PIN AB30 [get_ports AUD_SCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDA]
+set_property PACKAGE_PIN AA29 [get_ports AUD_SDA]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDIN]
+set_property PACKAGE_PIN AA30 [get_ports AUD_SDIN]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDOUT]
+set_property PACKAGE_PIN Y27 [get_ports AUD_SDOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nPOR]
+set_property PACKAGE_PIN AU22 [get_ports CB_nPOR]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nRST]
+set_property PACKAGE_PIN AV23 [get_ports CB_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_RUN]
+set_property PACKAGE_PIN AR25 [get_ports CB_RUN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_CLK]
+set_property PACKAGE_PIN AT20 [get_ports CFG_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAIN]
+set_property PACKAGE_PIN AT19 [get_ports CFG_DATAIN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAOUT]
+set_property PACKAGE_PIN AV18 [get_ports CFG_DATAOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_LOAD]
+set_property PACKAGE_PIN AW18 [get_ports CFG_LOAD]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_nRST]
+set_property PACKAGE_PIN AR20 [get_ports CFG_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AT18 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AJ16 [get_ports CLCD_BL]
+set_property PACKAGE_PIN AP15 [get_ports CLCD_CS]
+set_property PACKAGE_PIN AN17 [get_ports {CLCD_PD[10]}]
+set_property PACKAGE_PIN AP16 [get_ports {CLCD_PD[11]}]
+set_property PACKAGE_PIN AP18 [get_ports {CLCD_PD[12]}]
+set_property PACKAGE_PIN AR18 [get_ports {CLCD_PD[13]}]
+set_property PACKAGE_PIN AM16 [get_ports {CLCD_PD[14]}]
+set_property PACKAGE_PIN AN16 [get_ports {CLCD_PD[15]}]
+set_property PACKAGE_PIN AR17 [get_ports {CLCD_PD[16]}]
+set_property PACKAGE_PIN AR16 [get_ports {CLCD_PD[17]}]
+set_property PACKAGE_PIN AM15 [get_ports CLCD_RD]
+set_property PACKAGE_PIN AN14 [get_ports CLCD_RS]
+set_property PACKAGE_PIN AK18 [get_ports CLCD_RST]
+#set_property PACKAGE_PIN AN18 [get_ports CLCD_SDI]
+#set_property PACKAGE_PIN AH16 [get_ports CLCD_SDO]
+set_property PACKAGE_PIN AJ14 [get_ports CLCD_TINT]
+set_property PACKAGE_PIN AL17 [get_ports CLCD_TNC]
+set_property PACKAGE_PIN AL18 [get_ports CLCD_TSCL]
+set_property PACKAGE_PIN AJ15 [get_ports CLCD_TSDA]
+set_property PACKAGE_PIN AP14 [get_ports CLCD_WR_SCL]
+# not used
+# set_property PACKAGE_PIN N28 [get_ports {CLK_BIDIR_P[2]}]
+# set_property PACKAGE_PIN N29 [get_ports {CLK_BIDIR_N[2]}]
+# set_property PACKAGE_PIN E32 [get_ports {CLK_BIDIR_P[3]}]
+# set_property PACKAGE_PIN D33 [get_ports {CLK_BIDIR_N[3]}]
+# set_property PACKAGE_PIN G31 [get_ports {CLK_M2C_P[0]}]
+# set_property PACKAGE_PIN F32 [get_ports {CLK_M2C_N[0]}]
+# set_property PACKAGE_PIN E31 [get_ports {CLK_M2C_P[1]}]
+# set_property PACKAGE_PIN D31 [get_ports {CLK_M2C_N[1]}]
+set_property PACKAGE_PIN BB39 [get_ports CS_nDET]
+set_property PACKAGE_PIN BB36 [get_ports CS_nSRST]
+set_property PACKAGE_PIN BB37 [get_ports CS_nTRST]
+set_property PACKAGE_PIN AW33 [get_ports CS_T_CLK]
+set_property PACKAGE_PIN AY35 [get_ports CS_T_CTL]
+set_property PACKAGE_PIN AW34 [get_ports {CS_T_D[0]}]
+set_property PACKAGE_PIN AT34 [get_ports {CS_T_D[1]}]
+set_property PACKAGE_PIN AU34 [get_ports {CS_T_D[2]}]
+set_property PACKAGE_PIN AV36 [get_ports {CS_T_D[3]}]
+set_property PACKAGE_PIN AW36 [get_ports {CS_T_D[4]}]
+set_property PACKAGE_PIN AT35 [get_ports {CS_T_D[5]}]
+set_property PACKAGE_PIN AU35 [get_ports {CS_T_D[6]}]
+set_property PACKAGE_PIN AU36 [get_ports {CS_T_D[7]}]
+set_property PACKAGE_PIN AV37 [get_ports {CS_T_D[8]}]
+set_property PACKAGE_PIN AW35 [get_ports {CS_T_D[9]}]
+set_property PACKAGE_PIN AY36 [get_ports {CS_T_D[10]}]
+set_property PACKAGE_PIN AY37 [get_ports {CS_T_D[11]}]
+set_property PACKAGE_PIN BB34 [get_ports {CS_T_D[12]}]
+set_property PACKAGE_PIN BB35 [get_ports {CS_T_D[13]}]
+set_property PACKAGE_PIN BA37 [get_ports {CS_T_D[14]}]
+set_property PACKAGE_PIN BA38 [get_ports {CS_T_D[15]}]
+set_property PACKAGE_PIN AV33 [get_ports CS_TCK]
+set_property PACKAGE_PIN BA35 [get_ports CS_TDI]
+set_property PACKAGE_PIN AW38 [get_ports CS_TDO]
+set_property PACKAGE_PIN AY38 [get_ports CS_TMS]
+# not used
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[0]}]
+#set_property PACKAGE_PIN J19 [get_ports {DDR_CHIPID[0]}]
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[1]}]
+#set_property PACKAGE_PIN G20 [get_ports {DDR_CHIPID[1]}]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nALERT]
+#set_property PACKAGE_PIN P15 [get_ports DDR_nALERT]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nEVENT]
+#set_property PACKAGE_PIN C17 [get_ports DDR_nEVENT]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_PARITY]
+# set_property PACKAGE_PIN D18 [get_ports DDR_PARITY]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SCL]
+# set_property PACKAGE_PIN N21 [get_ports DDR_SCL]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SDA]
+# set_property PACKAGE_PIN P21 [get_ports DDR_SDA]
+# set_property PACKAGE_PIN AC42 [get_ports {DP_M2C_N[0]}]
+# set_property PACKAGE_PIN AJ42 [get_ports {DP_M2C_N[1]}]
+# set_property PACKAGE_PIN AE42 [get_ports {DP_M2C_N[2]}]
+# set_property PACKAGE_PIN W42 [get_ports {DP_M2C_N[3]}]
+# set_property PACKAGE_PIN R42 [get_ports {DP_M2C_N[4]}]
+# set_property PACKAGE_PIN L42 [get_ports {DP_M2C_N[5]}]
+# set_property PACKAGE_PIN N42 [get_ports {DP_M2C_N[6]}]
+# set_property PACKAGE_PIN U42 [get_ports {DP_M2C_N[7]}]
+# set_property PACKAGE_PIN AA42 [get_ports {DP_M2C_N[8]}]
+# set_property PACKAGE_PIN AG42 [get_ports {DP_M2C_N[9]}]
+# set_property PACKAGE_PIN AC41 [get_ports {DP_M2C_P[0]}]
+# set_property PACKAGE_PIN AJ41 [get_ports {DP_M2C_P[1]}]
+# set_property PACKAGE_PIN AE41 [get_ports {DP_M2C_P[2]}]
+# set_property PACKAGE_PIN W41 [get_ports {DP_M2C_P[3]}]
+# set_property PACKAGE_PIN R41 [get_ports {DP_M2C_P[4]}]
+# set_property PACKAGE_PIN L41 [get_ports {DP_M2C_P[5]}]
+# set_property PACKAGE_PIN N41 [get_ports {DP_M2C_P[6]}]
+# set_property PACKAGE_PIN U41 [get_ports {DP_M2C_P[7]}]
+# set_property PACKAGE_PIN AA41 [get_ports {DP_M2C_P[8]}]
+# set_property PACKAGE_PIN AG41 [get_ports {DP_M2C_P[9]}]
+set_property PACKAGE_PIN AG34 [get_ports HDMI_CSCL]
+set_property PACKAGE_PIN AE33 [get_ports HDMI_CSDA]
+set_property PACKAGE_PIN AF33 [get_ports HDMI_INT]
+set_property PACKAGE_PIN W29 [get_ports EMMC_CLK]
+set_property PACKAGE_PIN AC34 [get_ports EMMC_CMD]
+set_property PACKAGE_PIN Y32 [get_ports {EMMC_DAT[0]}]
+set_property PACKAGE_PIN Y33 [get_ports {EMMC_DAT[1]}]
+set_property PACKAGE_PIN W33 [get_ports {EMMC_DAT[2]}]
+set_property PACKAGE_PIN W34 [get_ports {EMMC_DAT[3]}]
+set_property PACKAGE_PIN AA34 [get_ports {EMMC_DAT[4]}]
+set_property PACKAGE_PIN AB34 [get_ports {EMMC_DAT[5]}]
+set_property PACKAGE_PIN W31 [get_ports {EMMC_DAT[6]}]
+set_property PACKAGE_PIN Y31 [get_ports {EMMC_DAT[7]}]
+set_property PACKAGE_PIN AE32 [get_ports EMMC_DS]
+set_property PACKAGE_PIN W30 [get_ports EMMC_nRST]
+set_property PACKAGE_PIN AK23 [get_ports ETH_INT]
+set_property PACKAGE_PIN AL24 [get_ports ETH_nCS]
+set_property PACKAGE_PIN AJ23 [get_ports ETH_nOE]
+# not used
+# set_property PACKAGE_PIN AV38 [get_ports FMC_CLK_DIR]
+# set_property PACKAGE_PIN AL42 [get_ports FMC_nPRSNT]
+# set_property PACKAGE_PIN BB40 [get_ports {HA_N[2]}]
+# set_property PACKAGE_PIN BA41 [get_ports {HA_N[3]}]
+# set_property PACKAGE_PIN AY40 [get_ports {HA_N[4]}]
+# set_property PACKAGE_PIN AU42 [get_ports {HA_N[5]}]
+# set_property PACKAGE_PIN AY42 [get_ports {HA_N[6]}]
+# set_property PACKAGE_PIN AW41 [get_ports {HA_N[7]}]
+# set_property PACKAGE_PIN AU37 [get_ports {HA_N[8]}]
+# set_property PACKAGE_PIN AT42 [get_ports {HA_N[9]}]
+# set_property PACKAGE_PIN AT38 [get_ports {HA_N[10]}]
+# set_property PACKAGE_PIN AV42 [get_ports {HA_N[11]}]
+# set_property PACKAGE_PIN AR37 [get_ports {HA_N[12]}]
+# set_property PACKAGE_PIN AN42 [get_ports {HA_N[13]}]
+# set_property PACKAGE_PIN AP38 [get_ports {HA_N[14]}]
+# set_property PACKAGE_PIN AN37 [get_ports {HA_N[15]}]
+# set_property PACKAGE_PIN AM42 [get_ports {HA_N[16]}]
+# set_property PACKAGE_PIN AR41 [get_ports {HA_N[18]}]
+# set_property PACKAGE_PIN AM39 [get_ports {HA_N[19]}]
+# set_property PACKAGE_PIN AR40 [get_ports {HA_N[20]}]
+# set_property PACKAGE_PIN AM40 [get_ports {HA_N[21]}]
+# set_property PACKAGE_PIN AK38 [get_ports {HA_N[22]}]
+# set_property PACKAGE_PIN AL38 [get_ports {HA_N[23]}]
+# set_property PACKAGE_PIN AT39 [get_ports {HA_P[0]}]
+# set_property PACKAGE_PIN AT40 [get_ports {HA_N[0]}]
+# set_property PACKAGE_PIN AU39 [get_ports {HA_P[1]}]
+# set_property PACKAGE_PIN AU40 [get_ports {HA_N[1]}]
+# set_property PACKAGE_PIN BA39 [get_ports {HA_P[2]}]
+# set_property PACKAGE_PIN BA40 [get_ports {HA_P[3]}]
+# set_property PACKAGE_PIN AW39 [get_ports {HA_P[4]}]
+# set_property PACKAGE_PIN AU41 [get_ports {HA_P[5]}]
+# set_property PACKAGE_PIN AY41 [get_ports {HA_P[6]}]
+# set_property PACKAGE_PIN AW40 [get_ports {HA_P[7]}]
+# set_property PACKAGE_PIN AT37 [get_ports {HA_P[8]}]
+# set_property PACKAGE_PIN AR42 [get_ports {HA_P[9]}]
+# set_property PACKAGE_PIN AR38 [get_ports {HA_P[10]}]
+# set_property PACKAGE_PIN AV41 [get_ports {HA_P[11]}]
+# set_property PACKAGE_PIN AR36 [get_ports {HA_P[12]}]
+# set_property PACKAGE_PIN AN41 [get_ports {HA_P[13]}]
+# set_property PACKAGE_PIN AN38 [get_ports {HA_P[14]}]
+# set_property PACKAGE_PIN AM37 [get_ports {HA_P[15]}]
+# set_property PACKAGE_PIN AM41 [get_ports {HA_P[16]}]
+# set_property PACKAGE_PIN AN39 [get_ports {HA_P[17]}]
+# set_property PACKAGE_PIN AP39 [get_ports {HA_N[17]}]
+# set_property PACKAGE_PIN AP41 [get_ports {HA_P[18]}]
+# set_property PACKAGE_PIN AL39 [get_ports {HA_P[19]}]
+# set_property PACKAGE_PIN AP40 [get_ports {HA_P[20]}]
+# set_property PACKAGE_PIN AL40 [get_ports {HA_P[21]}]
+# set_property PACKAGE_PIN AK37 [get_ports {HA_P[22]}]
+# set_property PACKAGE_PIN AL37 [get_ports {HA_P[23]}]
+# set_property PACKAGE_PIN T32 [get_ports {HB_N[1]}]
+# set_property PACKAGE_PIN V33 [get_ports {HB_N[2]}]
+# set_property PACKAGE_PIN V29 [get_ports {HB_N[3]}]
+# set_property PACKAGE_PIN T30 [get_ports {HB_N[4]}]
+# set_property PACKAGE_PIN T34 [get_ports {HB_N[5]}]
+# set_property PACKAGE_PIN R32 [get_ports {HB_N[7]}]
+# set_property PACKAGE_PIN P29 [get_ports {HB_N[8]}]
+# set_property PACKAGE_PIN P30 [get_ports {HB_N[9]}]
+# set_property PACKAGE_PIN K28 [get_ports {HB_N[10]}]
+# set_property PACKAGE_PIN L29 [get_ports {HB_N[11]}]
+# set_property PACKAGE_PIN K31 [get_ports {HB_N[12]}]
+# set_property PACKAGE_PIN L33 [get_ports {HB_N[13]}]
+# set_property PACKAGE_PIN U31 [get_ports {HB_N[14]}]
+# set_property PACKAGE_PIN N33 [get_ports {HB_N[15]}]
+# set_property PACKAGE_PIN L34 [get_ports {HB_N[16]}]
+# set_property PACKAGE_PIN R28 [get_ports {HB_N[18]}]
+# set_property PACKAGE_PIN N27 [get_ports {HB_N[19]}]
+# set_property PACKAGE_PIN U34 [get_ports {HB_N[20]}]
+# set_property PACKAGE_PIN N34 [get_ports {HB_N[21]}]
+# set_property PACKAGE_PIN N31 [get_ports {HB_P[0]}]
+# set_property PACKAGE_PIN M31 [get_ports {HB_N[0]}]
+# set_property PACKAGE_PIN U32 [get_ports {HB_P[1]}]
+# set_property PACKAGE_PIN V32 [get_ports {HB_P[2]}]
+# set_property PACKAGE_PIN V28 [get_ports {HB_P[3]}]
+# set_property PACKAGE_PIN U30 [get_ports {HB_P[4]}]
+# set_property PACKAGE_PIN T33 [get_ports {HB_P[5]}]
+# set_property PACKAGE_PIN M30 [get_ports {HB_P[6]}]
+# set_property PACKAGE_PIN L30 [get_ports {HB_N[6]}]
+# set_property PACKAGE_PIN R31 [get_ports {HB_P[7]}]
+# set_property PACKAGE_PIN P28 [get_ports {HB_P[8]}]
+# set_property PACKAGE_PIN R30 [get_ports {HB_P[9]}]
+# set_property PACKAGE_PIN L28 [get_ports {HB_P[10]}]
+# set_property PACKAGE_PIN M29 [get_ports {HB_P[11]}]
+# set_property PACKAGE_PIN K30 [get_ports {HB_P[12]}]
+# set_property PACKAGE_PIN L32 [get_ports {HB_P[13]}]
+# set_property PACKAGE_PIN V31 [get_ports {HB_P[14]}]
+# set_property PACKAGE_PIN P33 [get_ports {HB_P[15]}]
+# set_property PACKAGE_PIN M34 [get_ports {HB_P[16]}]
+# set_property PACKAGE_PIN N32 [get_ports {HB_P[17]}]
+# set_property PACKAGE_PIN M32 [get_ports {HB_N[17]}]
+# set_property PACKAGE_PIN T28 [get_ports {HB_P[18]}]
+# set_property PACKAGE_PIN N26 [get_ports {HB_P[19]}]
+# set_property PACKAGE_PIN V34 [get_ports {HB_P[20]}]
+# set_property PACKAGE_PIN P34 [get_ports {HB_P[21]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {CLK_CFG}]
+# set_property PACKAGE_PIN AT27 [get_ports {CLK_CFG}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_CSIB}]
+# set_property PACKAGE_PIN BA27 [get_ports {IOFPGA_CSIB}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[4]}]
+# set_property PACKAGE_PIN AV26 [get_ports {IOFPGA_D[4]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[5]}]
+# set_property PACKAGE_PIN AV27 [get_ports {IOFPGA_D[5]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[6]}]
+# set_property PACKAGE_PIN AU29 [get_ports {IOFPGA_D[6]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[7]}]
+# set_property PACKAGE_PIN AV29 [get_ports {IOFPGA_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NRST]
+set_property PACKAGE_PIN AV31 [get_ports IOFPGA_NRST]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NSPIR]
+set_property PACKAGE_PIN AV32 [get_ports IOFPGA_NSPIR]
+set_property IOSTANDARD LVCMOS33 [get_ports IOFPGA_SYSWDT]
+set_property PACKAGE_PIN AU20 [get_ports IOFPGA_SYSWDT]
+# not used
+# set_property PACKAGE_PIN AN27 [get_ports {LA_N[2]}]
+# set_property PACKAGE_PIN AP30 [get_ports {LA_N[3]}]
+# set_property PACKAGE_PIN AN29 [get_ports {LA_N[4]}]
+# set_property PACKAGE_PIN AR35 [get_ports {LA_N[5]}]
+# set_property PACKAGE_PIN AR33 [get_ports {LA_N[6]}]
+# set_property PACKAGE_PIN AN32 [get_ports {LA_N[7]}]
+# set_property PACKAGE_PIN AP31 [get_ports {LA_N[8]}]
+# set_property PACKAGE_PIN AN34 [get_ports {LA_N[9]}]
+# set_property PACKAGE_PIN AL35 [get_ports {LA_N[10]}]
+# set_property PACKAGE_PIN AM36 [get_ports {LA_N[11]}]
+# set_property PACKAGE_PIN AP34 [get_ports {LA_N[12]}]
+# set_property PACKAGE_PIN AL32 [get_ports {LA_N[13]}]
+# set_property PACKAGE_PIN AK36 [get_ports {LA_N[14]}]
+# set_property PACKAGE_PIN AJ34 [get_ports {LA_N[15]}]
+# set_property PACKAGE_PIN AL33 [get_ports {LA_N[16]}]
+# set_property PACKAGE_PIN AJ29 [get_ports {LA_N[19]}]
+# set_property PACKAGE_PIN AJ33 [get_ports {LA_N[20]}]
+# set_property PACKAGE_PIN AH29 [get_ports {LA_N[21]}]
+# set_property PACKAGE_PIN AH31 [get_ports {LA_N[22]}]
+# set_property PACKAGE_PIN AG30 [get_ports {LA_N[23]}]
+# set_property PACKAGE_PIN G32 [get_ports {LA_N[24]}]
+# set_property PACKAGE_PIN H34 [get_ports {LA_N[25]}]
+# set_property PACKAGE_PIN H31 [get_ports {LA_N[26]}]
+# set_property PACKAGE_PIN K33 [get_ports {LA_N[27]}]
+# set_property PACKAGE_PIN H29 [get_ports {LA_N[28]}]
+# set_property PACKAGE_PIN H33 [get_ports {LA_N[29]}]
+# set_property PACKAGE_PIN F34 [get_ports {LA_N[30]}]
+# set_property PACKAGE_PIN E33 [get_ports {LA_N[31]}]
+# set_property PACKAGE_PIN C34 [get_ports {LA_N[32]}]
+# set_property PACKAGE_PIN G30 [get_ports {LA_N[33]}]
+# set_property PACKAGE_PIN AM29 [get_ports {LA_P[0]}]
+# set_property PACKAGE_PIN AM30 [get_ports {LA_N[0]}]
+# set_property PACKAGE_PIN AL29 [get_ports {LA_P[1]}]
+# set_property PACKAGE_PIN AL30 [get_ports {LA_N[1]}]
+# set_property PACKAGE_PIN AM27 [get_ports {LA_P[2]}]
+# set_property PACKAGE_PIN AP29 [get_ports {LA_P[3]}]
+# set_property PACKAGE_PIN AN28 [get_ports {LA_P[4]}]
+# set_property PACKAGE_PIN AP35 [get_ports {LA_P[5]}]
+# set_property PACKAGE_PIN AP33 [get_ports {LA_P[6]}]
+# set_property PACKAGE_PIN AM32 [get_ports {LA_P[7]}]
+# set_property PACKAGE_PIN AN31 [get_ports {LA_P[8]}]
+# set_property PACKAGE_PIN AM34 [get_ports {LA_P[9]}]
+# set_property PACKAGE_PIN AL34 [get_ports {LA_P[10]}]
+# set_property PACKAGE_PIN AM35 [get_ports {LA_P[11]}]
+# set_property PACKAGE_PIN AN33 [get_ports {LA_P[12]}]
+# set_property PACKAGE_PIN AK32 [get_ports {LA_P[13]}]
+# set_property PACKAGE_PIN AK35 [get_ports {LA_P[14]}]
+# set_property PACKAGE_PIN AH34 [get_ports {LA_P[15]}]
+# set_property PACKAGE_PIN AK33 [get_ports {LA_P[16]}]
+# set_property PACKAGE_PIN AK30 [get_ports {LA_P[17]}]
+# set_property PACKAGE_PIN AK31 [get_ports {LA_N[17]}]
+# set_property PACKAGE_PIN AJ30 [get_ports {LA_P[18]}]
+# set_property PACKAGE_PIN AJ31 [get_ports {LA_N[18]}]
+# set_property PACKAGE_PIN AJ28 [get_ports {LA_P[19]}]
+# set_property PACKAGE_PIN AH33 [get_ports {LA_P[20]}]
+# set_property PACKAGE_PIN AH28 [get_ports {LA_P[21]}]
+# set_property PACKAGE_PIN AG31 [get_ports {LA_P[22]}]
+# set_property PACKAGE_PIN AG29 [get_ports {LA_P[23]}]
+# set_property PACKAGE_PIN H32 [get_ports {LA_P[24]}]
+# set_property PACKAGE_PIN J34 [get_ports {LA_P[25]}]
+# set_property PACKAGE_PIN J30 [get_ports {LA_P[26]}]
+# set_property PACKAGE_PIN K32 [get_ports {LA_P[27]}]
+# set_property PACKAGE_PIN J29 [get_ports {LA_P[28]}]
+# set_property PACKAGE_PIN J33 [get_ports {LA_P[29]}]
+# set_property PACKAGE_PIN G34 [get_ports {LA_P[30]}]
+# set_property PACKAGE_PIN F33 [get_ports {LA_P[31]}]
+# set_property PACKAGE_PIN D34 [get_ports {LA_P[32]}]
+# set_property PACKAGE_PIN G29 [get_ports {LA_P[33]}]
+set_property PACKAGE_PIN AM17 [get_ports {MMB_DATA[0]}]
+set_property PACKAGE_PIN AL14 [get_ports {MMB_DATA[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {MMB_DATA[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {MMB_DATA[3]}]
+set_property PACKAGE_PIN AM14 [get_ports {MMB_DATA[4]}]
+set_property PACKAGE_PIN AN13 [get_ports {MMB_DATA[5]}]
+set_property PACKAGE_PIN AM11 [get_ports {MMB_DATA[6]}]
+set_property PACKAGE_PIN AN11 [get_ports {MMB_DATA[7]}]
+set_property PACKAGE_PIN AR13 [get_ports {MMB_DATA[8]}]
+set_property PACKAGE_PIN AR12 [get_ports {MMB_DATA[9]}]
+set_property PACKAGE_PIN AL10 [get_ports {MMB_DATA[10]}]
+set_property PACKAGE_PIN AM10 [get_ports {MMB_DATA[11]}]
+set_property PACKAGE_PIN AM12 [get_ports {MMB_DATA[12]}]
+set_property PACKAGE_PIN AN12 [get_ports {MMB_DATA[13]}]
+set_property PACKAGE_PIN AP13 [get_ports {MMB_DATA[14]}]
+set_property PACKAGE_PIN AK13 [get_ports {MMB_DATA[15]}]
+set_property PACKAGE_PIN AK12 [get_ports {MMB_DATA[16]}]
+set_property PACKAGE_PIN AK11 [get_ports {MMB_DATA[17]}]
+set_property PACKAGE_PIN AK10 [get_ports {MMB_DATA[18]}]
+set_property PACKAGE_PIN AH13 [get_ports {MMB_DATA[19]}]
+set_property PACKAGE_PIN AJ13 [get_ports {MMB_DATA[20]}]
+set_property PACKAGE_PIN AJ11 [get_ports {MMB_DATA[21]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MMB_DATA[22]}]
+set_property PACKAGE_PIN AH12 [get_ports {MMB_DATA[23]}]
+set_property PACKAGE_PIN AH11 [get_ports MMB_DE]
+set_property PACKAGE_PIN AG12 [get_ports MMB_HS]
+set_property PACKAGE_PIN AH14 [get_ports MMB_IDCLK]
+set_property PACKAGE_PIN AF29 [get_ports MMB_SCK]
+set_property PACKAGE_PIN AC28 [get_ports {MMB_SD[0]}]
+set_property PACKAGE_PIN AC29 [get_ports {MMB_SD[1]}]
+set_property PACKAGE_PIN AE27 [get_ports {MMB_SD[2]}]
+set_property PACKAGE_PIN AF34 [get_ports {MMB_SD[3]}]
+set_property PACKAGE_PIN AG11 [get_ports MMB_VS]
+set_property PACKAGE_PIN AF30 [get_ports MMB_WS]
+set_property PACKAGE_PIN AL15 [get_ports {OSCCLK[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {OSCCLK[1]}]
+set_property PACKAGE_PIN AY32 [get_ports {OSCCLK[2]}]
+set_property PACKAGE_PIN AY30 [get_ports {OSCCLK[3]}]
+set_property PACKAGE_PIN AC31 [get_ports {OSCCLK[4]}]
+set_property PACKAGE_PIN AC32 [get_ports {OSCCLK[5]}]
+set_property PACKAGE_PIN AT29 [get_ports PB_IRQ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D0]
+set_property PACKAGE_PIN AU24 [get_ports QSPI_D0]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D1]
+set_property PACKAGE_PIN AV24 [get_ports QSPI_D1]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D2]
+set_property PACKAGE_PIN AV21 [get_ports QSPI_D2]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D3]
+set_property PACKAGE_PIN AV22 [get_ports QSPI_D3]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_nCS]
+set_property PACKAGE_PIN AT24 [get_ports QSPI_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_SCLK]
+set_property PACKAGE_PIN AT25 [get_ports QSPI_SCLK]
+# not used
+# set_property PACKAGE_PIN AL13 [get_ports SATA_CLK_P]
+# set_property PACKAGE_PIN AL12 [get_ports SATA_CLK_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[0]}]
+set_property PACKAGE_PIN AW14 [get_ports {SH0_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[1]}]
+set_property PACKAGE_PIN AW13 [get_ports {SH0_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[2]}]
+set_property PACKAGE_PIN AW15 [get_ports {SH0_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[3]}]
+set_property PACKAGE_PIN AY15 [get_ports {SH0_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[4]}]
+set_property PACKAGE_PIN AY13 [get_ports {SH0_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[5]}]
+set_property PACKAGE_PIN AY12 [get_ports {SH0_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[6]}]
+set_property PACKAGE_PIN BA15 [get_ports {SH0_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[7]}]
+set_property PACKAGE_PIN BB14 [get_ports {SH0_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[8]}]
+set_property PACKAGE_PIN BA12 [get_ports {SH0_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[9]}]
+set_property PACKAGE_PIN BB12 [get_ports {SH0_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[10]}]
+set_property PACKAGE_PIN BA14 [get_ports {SH0_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[11]}]
+set_property PACKAGE_PIN BA13 [get_ports {SH0_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[12]}]
+set_property PACKAGE_PIN BB15 [get_ports {SH0_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[13]}]
+set_property PACKAGE_PIN AU12 [get_ports {SH0_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[14]}]
+set_property PACKAGE_PIN AV12 [get_ports {SH0_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[15]}]
+set_property PACKAGE_PIN AV17 [get_ports {SH0_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[16]}]
+set_property PACKAGE_PIN AV16 [get_ports {SH0_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[17]}]
+set_property PACKAGE_PIN AT14 [get_ports {SH0_IO[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {SH1_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[1]}]
+set_property PACKAGE_PIN AU17 [get_ports {SH1_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[2]}]
+set_property PACKAGE_PIN AV19 [get_ports {SH1_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[3]}]
+set_property PACKAGE_PIN AW19 [get_ports {SH1_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[4]}]
+set_property PACKAGE_PIN AW20 [get_ports {SH1_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[5]}]
+set_property PACKAGE_PIN BA19 [get_ports {SH1_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[6]}]
+set_property PACKAGE_PIN BA18 [get_ports {SH1_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[7]}]
+set_property PACKAGE_PIN AY20 [get_ports {SH1_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[8]}]
+set_property PACKAGE_PIN BA20 [get_ports {SH1_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[9]}]
+set_property PACKAGE_PIN BA17 [get_ports {SH1_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[10]}]
+set_property PACKAGE_PIN BB17 [get_ports {SH1_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[11]}]
+set_property PACKAGE_PIN BB20 [get_ports {SH1_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[12]}]
+set_property PACKAGE_PIN BB19 [get_ports {SH1_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[13]}]
+set_property PACKAGE_PIN AW16 [get_ports {SH1_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[14]}]
+set_property PACKAGE_PIN AY16 [get_ports {SH1_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[15]}]
+set_property PACKAGE_PIN AY18 [get_ports {SH1_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[16]}]
+set_property PACKAGE_PIN AY17 [get_ports {SH1_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN BB16 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN AL25 [get_ports SH_ADC_CK]
+set_property PACKAGE_PIN AM25 [get_ports SH_ADC_CS]
+set_property PACKAGE_PIN AP25 [get_ports SH_ADC_DI]
+set_property PACKAGE_PIN AP26 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS33 [get_ports SH_nRST]
+set_property PACKAGE_PIN AU14 [get_ports SH_nRST]
+set_property PACKAGE_PIN AK20 [get_ports {SMBF_ADDR[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {SMBF_ADDR[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {SMBF_ADDR[2]}]
+set_property PACKAGE_PIN AJ19 [get_ports {SMBF_ADDR[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {SMBF_ADDR[4]}]
+set_property PACKAGE_PIN AJ21 [get_ports {SMBF_ADDR[5]}]
+set_property PACKAGE_PIN AH19 [get_ports {SMBF_ADDR[6]}]
+set_property PACKAGE_PIN AK22 [get_ports {SMBF_DATA[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {SMBF_DATA[1]}]
+set_property PACKAGE_PIN AL19 [get_ports {SMBF_DATA[2]}]
+set_property PACKAGE_PIN AL20 [get_ports {SMBF_DATA[3]}]
+set_property PACKAGE_PIN AH18 [get_ports {SMBF_DATA[4]}]
+set_property PACKAGE_PIN AM19 [get_ports {SMBF_DATA[5]}]
+set_property PACKAGE_PIN AN19 [get_ports {SMBF_DATA[6]}]
+set_property PACKAGE_PIN AP19 [get_ports {SMBF_DATA[7]}]
+set_property PACKAGE_PIN AP20 [get_ports {SMBF_DATA[8]}]
+set_property PACKAGE_PIN AM20 [get_ports {SMBF_DATA[9]}]
+set_property PACKAGE_PIN AN21 [get_ports {SMBF_DATA[10]}]
+set_property PACKAGE_PIN AP21 [get_ports {SMBF_DATA[11]}]
+set_property PACKAGE_PIN AR22 [get_ports {SMBF_DATA[12]}]
+set_property PACKAGE_PIN AM21 [get_ports {SMBF_DATA[13]}]
+set_property PACKAGE_PIN AM22 [get_ports {SMBF_DATA[14]}]
+set_property PACKAGE_PIN AN22 [get_ports {SMBF_DATA[15]}]
+set_property PACKAGE_PIN AJ20 [get_ports SMBF_FIFOSEL]
+set_property PACKAGE_PIN AN23 [get_ports SMBF_nOE]
+set_property PACKAGE_PIN AL23 [get_ports SMBF_nRST]
+set_property PACKAGE_PIN AP23 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[16]}]
+set_property PACKAGE_PIN AR26 [get_ports {SMBM_A[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[17]}]
+set_property PACKAGE_PIN AT22 [get_ports {SMBM_A[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[18]}]
+set_property PACKAGE_PIN AT23 [get_ports {SMBM_A[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[19]}]
+set_property PACKAGE_PIN AU21 [get_ports {SMBM_A[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[20]}]
+set_property PACKAGE_PIN AY22 [get_ports {SMBM_A[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[21]}]
+set_property PACKAGE_PIN BA22 [get_ports {SMBM_A[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[22]}]
+set_property PACKAGE_PIN AW21 [get_ports {SMBM_A[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[23]}]
+set_property PACKAGE_PIN AY21 [get_ports {SMBM_A[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[24]}]
+set_property PACKAGE_PIN BA23 [get_ports {SMBM_A[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[25]}]
+set_property PACKAGE_PIN BA24 [get_ports {SMBM_A[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_CLK]
+set_property PACKAGE_PIN AY25 [get_ports SMBM_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[0]}]
+set_property PACKAGE_PIN BB21 [get_ports {SMBM_D[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[1]}]
+set_property PACKAGE_PIN BB22 [get_ports {SMBM_D[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[2]}]
+set_property PACKAGE_PIN AW24 [get_ports {SMBM_D[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {SMBM_D[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[4]}]
+set_property PACKAGE_PIN AW23 [get_ports {SMBM_D[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[5]}]
+set_property PACKAGE_PIN AY23 [get_ports {SMBM_D[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[6]}]
+set_property PACKAGE_PIN BB24 [get_ports {SMBM_D[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[7]}]
+set_property PACKAGE_PIN AY27 [get_ports {SMBM_D[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[8]}]
+set_property PACKAGE_PIN AY26 [get_ports {SMBM_D[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[9]}]
+set_property PACKAGE_PIN AY28 [get_ports {SMBM_D[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[10]}]
+set_property PACKAGE_PIN BA28 [get_ports {SMBM_D[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[11]}]
+set_property PACKAGE_PIN BA25 [get_ports {SMBM_D[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[12]}]
+set_property PACKAGE_PIN BB25 [get_ports {SMBM_D[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[13]}]
+set_property PACKAGE_PIN AW28 [get_ports {SMBM_D[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[14]}]
+set_property PACKAGE_PIN AW29 [get_ports {SMBM_D[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[15]}]
+set_property PACKAGE_PIN BB26 [get_ports {SMBM_D[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[0]}]
+set_property PACKAGE_PIN AU26 [get_ports {SMBM_nBL[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[1]}]
+set_property PACKAGE_PIN AR28 [get_ports {SMBM_nBL[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[1]}]
+set_property PACKAGE_PIN BB27 [get_ports {SMBM_nE[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[2]}]
+set_property PACKAGE_PIN AU27 [get_ports {SMBM_nE[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[3]}]
+set_property PACKAGE_PIN AV28 [get_ports {SMBM_nE[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[4]}]
+set_property PACKAGE_PIN AU25 [get_ports {SMBM_nE[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nOE]
+set_property PACKAGE_PIN AT28 [get_ports SMBM_nOE]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWAIT]
+set_property PACKAGE_PIN AP28 [get_ports SMBM_nWAIT]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AR27 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AF28 [get_ports {UART_RX_F[0]}]
+set_property PACKAGE_PIN AE31 [get_ports {UART_RX_F[1]}]
+set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
+set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
+set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
+set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
+set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
+set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
+set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
+set_property PACKAGE_PIN AP24 [get_ports USB_INT]
+set_property PACKAGE_PIN AM26 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CLK]
+set_property PACKAGE_PIN AU15 [get_ports USD_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CMD]
+set_property PACKAGE_PIN AU16 [get_ports USD_CMD]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[0]}]
+set_property PACKAGE_PIN AV14 [get_ports {USD_DAT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[1]}]
+set_property PACKAGE_PIN AV13 [get_ports {USD_DAT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[2]}]
+set_property PACKAGE_PIN AT13 [get_ports {USD_DAT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {USD_DAT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_NCD]
+set_property PACKAGE_PIN AT15 [get_ports USD_NCD]
+set_property PACKAGE_PIN AU32 [get_ports {USER_nLED[0]}]
+set_property PACKAGE_PIN AU30 [get_ports {USER_nLED[1]}]
+set_property PACKAGE_PIN AU31 [get_ports {USER_nLED[2]}]
+set_property PACKAGE_PIN AR32 [get_ports {USER_nLED[3]}]
+set_property PACKAGE_PIN AT33 [get_ports {USER_nLED[4]}]
+set_property PACKAGE_PIN AW30 [get_ports {USER_nLED[5]}]
+set_property PACKAGE_PIN AW31 [get_ports {USER_nLED[6]}]
+set_property PACKAGE_PIN AR30 [get_ports {USER_nLED[7]}]
+set_property PACKAGE_PIN BB31 [get_ports {USER_nLED[8]}]
+set_property PACKAGE_PIN BB32 [get_ports {USER_nLED[9]}]
+set_property PACKAGE_PIN AT30 [get_ports {USER_nPB[0]}]
+set_property PACKAGE_PIN AT32 [get_ports {USER_nPB[1]}]
+set_property PACKAGE_PIN BA29 [get_ports {USER_SW[0]}]
+set_property PACKAGE_PIN BB29 [get_ports {USER_SW[1]}]
+set_property PACKAGE_PIN BA32 [get_ports {USER_SW[2]}]
+set_property PACKAGE_PIN BA33 [get_ports {USER_SW[3]}]
+set_property PACKAGE_PIN BA30 [get_ports {USER_SW[4]}]
+set_property PACKAGE_PIN BB30 [get_ports {USER_SW[5]}]
+set_property PACKAGE_PIN AY33 [get_ports {USER_SW[6]}]
+set_property PACKAGE_PIN AY31 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports WDOG_RREQ]
+set_property PACKAGE_PIN AU19 [get_ports WDOG_RREQ]
+
+# native DDR pin names
+
+# set_property PACKAGE_PIN A17 [get_ports {c0_ddr4_dq[37]}]
+# set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[54]}]
+# set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[55]}]
+# set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_dq[28]}]
+# set_property PACKAGE_PIN D23 [get_ports {c0_ddr4_dq[52]}]
+# set_property PACKAGE_PIN D24 [get_ports {c0_ddr4_dq[53]}]
+# set_property PACKAGE_PIN C24 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+# set_property PACKAGE_PIN A22 [get_ports {c0_ddr4_dq[46]}]
+# set_property PACKAGE_PIN A23 [get_ports {c0_ddr4_dq[47]}]
+# set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_dq[29]}]
+# set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_dq[27]}]
+# set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dqs_t[6]}]
+# set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dqs_c[6]}]
+# set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dq[50]}]
+# set_property PACKAGE_PIN G21 [get_ports {c0_ddr4_dq[51]}]
+# set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+# set_property PACKAGE_PIN A24 [get_ports {c0_ddr4_dq[42]}]
+# set_property PACKAGE_PIN B22 [get_ports {c0_ddr4_dqs_t[5]}]
+# set_property PACKAGE_PIN B21 [get_ports {c0_ddr4_dqs_c[5]}]
+# set_property PACKAGE_PIN B17 [get_ports {c0_ddr4_dqs_t[4]}]
+# set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_dqs_c[4]}]
+# set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dq[38]}]
+# set_property PACKAGE_PIN A12 [get_ports {c0_ddr4_dq[31]}]
+# set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[48]}]
+# set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[49]}]
+# set_property PACKAGE_PIN C23 [get_ports {c0_ddr4_dq[40]}]
+# set_property PACKAGE_PIN A25 [get_ports {c0_ddr4_dq[43]}]
+# set_property PACKAGE_PIN C22 [get_ports {c0_ddr4_dq[44]}]
+# set_property PACKAGE_PIN B14 [get_ports {c0_ddr4_dq[24]}]
+# set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_adr[4]}]
+# set_property PACKAGE_PIN C21 [get_ports {c0_ddr4_dq[41]}]
+# set_property PACKAGE_PIN D21 [get_ports {c0_ddr4_dq[45]}]
+# set_property PACKAGE_PIN C16 [get_ports {c0_ddr4_dq[32]}]
+# set_property PACKAGE_PIN E12 [get_ports {c0_ddr4_dq[16]}]
+# set_property PACKAGE_PIN D13 [get_ports {c0_ddr4_dq[25]}]
+# set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_dqs_t[3]}]
+# set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_dqs_c[3]}]
+# set_property PACKAGE_PIN E15 [get_ports {c0_ddr4_dq[18]}]
+# #set_property PACKAGE_PIN P18 [get_ports {c0_ddr4_ck_t[1]}]
+# #set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_ck_c[1]}]
+# set_property PACKAGE_PIN L19 [get_ports {c0_ddr4_adr[0]}]
+# set_property PACKAGE_PIN J18 [get_ports {c0_ddr4_adr[5]}]
+# #set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke[0]}]
+# set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke}]
+# set_property PACKAGE_PIN D19 [get_ports c0_ddr4_act_n]
+# set_property PACKAGE_PIN F12 [get_ports {c0_ddr4_dq[17]}]
+# set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_dq[19]}]
+# set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_adr[2]}]
+# set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_adr[3]}]
+# set_property PACKAGE_PIN J16 [get_ports {c0_ddr4_adr[1]}]
+# #set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_cke[1]}]
+# set_property PACKAGE_PIN E18 [get_ports c0_ddr4_reset_n]
+# set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_dqs_t[2]}]
+# set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_dqs_c[2]}]
+# #set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t[0]}]
+# set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t}]
+# #set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c[0]}]
+# set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c}]
+# set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_bg[0]}]
+# #set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_bg[1]}]
+# #set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt[0]}]
+# set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt}]
+# #set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n[0]}]
+# set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n}]
+# #set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_cs_n[1]}]
+# #set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_odt[1]}]
+# set_property PACKAGE_PIN K13 [get_ports {c0_ddr4_dq[10]}]
+# set_property PACKAGE_PIN J14 [get_ports {c0_ddr4_dq[11]}]
+# set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_adr[16]}]
+# set_property PACKAGE_PIN G17 [get_ports {c0_ddr4_ba[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {c0_ddr4_adr[14]}]
+# set_property PACKAGE_PIN G19 [get_ports {c0_ddr4_ba[1]}]
+# set_property PACKAGE_PIN N11 [get_ports {c0_ddr4_dqs_t[0]}]
+# set_property PACKAGE_PIN M11 [get_ports {c0_ddr4_dqs_c[0]}]
+# set_property PACKAGE_PIN J15 [get_ports {c0_ddr4_dq[8]}]
+# set_property PACKAGE_PIN K15 [get_ports {c0_ddr4_dq[9]}]
+# set_property PACKAGE_PIN G16 [get_ports {c0_ddr4_adr[15]}]
+# set_property PACKAGE_PIN M10 [get_ports {c0_ddr4_dq[6]}]
+# set_property PACKAGE_PIN L10 [get_ports {c0_ddr4_dq[7]}]
+# set_property PACKAGE_PIN J11 [get_ports {c0_ddr4_dqs_t[1]}]
+# set_property PACKAGE_PIN J10 [get_ports {c0_ddr4_dqs_c[1]}]
+# set_property PACKAGE_PIN L17 [get_ports {c0_ddr4_adr[6]}]
+# set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_adr[8]}]
+# set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_adr[9]}]
+# set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_adr[7]}]
+# set_property PACKAGE_PIN M19 [get_ports {c0_ddr4_adr[10]}]
+# set_property PACKAGE_PIN M15 [get_ports {c0_ddr4_adr[11]}]
+# set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_adr[12]}]
+# set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_adr[13]}]
+# set_property PACKAGE_PIN L22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+# set_property PACKAGE_PIN P11 [get_ports {c0_ddr4_dq[0]}]
+# set_property PACKAGE_PIN P10 [get_ports {c0_ddr4_dq[1]}]
+# set_property PACKAGE_PIN L12 [get_ports {c0_ddr4_dq[2]}]
+# set_property PACKAGE_PIN M12 [get_ports {c0_ddr4_dq[3]}]
+# set_property PACKAGE_PIN N13 [get_ports {c0_ddr4_dq[4]}]
+# set_property PACKAGE_PIN N12 [get_ports {c0_ddr4_dq[5]}]
+# set_property PACKAGE_PIN K11 [get_ports {c0_ddr4_dq[12]}]
+# set_property PACKAGE_PIN K10 [get_ports {c0_ddr4_dq[13]}]
+# set_property PACKAGE_PIN J13 [get_ports {c0_ddr4_dq[14]}]
+# set_property PACKAGE_PIN K12 [get_ports {c0_ddr4_dq[15]}]
+# set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[20]}]
+# set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[21]}]
+# set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_dq[22]}]
+# set_property PACKAGE_PIN G14 [get_ports {c0_ddr4_dq[23]}]
+# set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_dq[26]}]
+# set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_dq[30]}]
+# set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[33]}]
+# set_property PACKAGE_PIN B19 [get_ports {c0_ddr4_dq[34]}]
+# set_property PACKAGE_PIN A20 [get_ports {c0_ddr4_dq[35]}]
+# set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[36]}]
+# set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dq[39]}]
+# set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[56]}]
+# set_property PACKAGE_PIN J23 [get_ports {c0_ddr4_dq[57]}]
+# set_property PACKAGE_PIN K20 [get_ports {c0_ddr4_dq[58]}]
+# set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dq[59]}]
+# set_property PACKAGE_PIN H21 [get_ports {c0_ddr4_dq[60]}]
+# set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[61]}]
+# set_property PACKAGE_PIN K23 [get_ports {c0_ddr4_dq[62]}]
+# set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[63]}]
+# set_property PACKAGE_PIN N14 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+# set_property PACKAGE_PIN L14 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+# set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+# set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+# set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+# set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dqs_t[7]}]
+
+#set_property CFGBVS GND [current_design]
+#set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# set_property PACKAGE_PIN H19 [get_ports c0_sys_clk_p]
+# set_property PACKAGE_PIN H18 [get_ports c0_sys_clk_n]
+
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[1]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[0]}]
+
+# set_property PACKAGE_PIN AB31 [get_ports GTX_CLK_P]
+# set_property PACKAGE_PIN AB32 [get_ports GTX_CLK_N]
+
+# set_property PACKAGE_PIN AH39 [get_ports {DP_C2M_N[0]}]
+# set_property PACKAGE_PIN AF39 [get_ports {DP_C2M_N[1]}]
+# set_property PACKAGE_PIN AD39 [get_ports {DP_C2M_N[2]}]
+# set_property PACKAGE_PIN AB39 [get_ports {DP_C2M_N[3]}]
+# set_property PACKAGE_PIN Y39 [get_ports {DP_C2M_N[4]}]
+# set_property PACKAGE_PIN V39 [get_ports {DP_C2M_N[5]}]
+# set_property PACKAGE_PIN K39 [get_ports {DP_C2M_N[6]}]
+# set_property PACKAGE_PIN M39 [get_ports {DP_C2M_N[7]}]
+# set_property PACKAGE_PIN P39 [get_ports {DP_C2M_N[8]}]
+# set_property PACKAGE_PIN T39 [get_ports {DP_C2M_N[9]}]
+# set_property PACKAGE_PIN AH38 [get_ports {DP_C2M_P[0]}]
+# set_property PACKAGE_PIN AF38 [get_ports {DP_C2M_P[1]}]
+# set_property PACKAGE_PIN AD38 [get_ports {DP_C2M_P[2]}]
+# set_property PACKAGE_PIN AB38 [get_ports {DP_C2M_P[3]}]
+# set_property PACKAGE_PIN Y38 [get_ports {DP_C2M_P[4]}]
+# set_property PACKAGE_PIN V38 [get_ports {DP_C2M_P[5]}]
+# set_property PACKAGE_PIN K38 [get_ports {DP_C2M_P[6]}]
+# set_property PACKAGE_PIN M38 [get_ports {DP_C2M_P[7]}]
+# set_property PACKAGE_PIN P38 [get_ports {DP_C2M_P[8]}]
+# set_property PACKAGE_PIN T38 [get_ports {DP_C2M_P[9]}]
+# set_property PACKAGE_PIN AE36 [get_ports {GBTCLK_M2C_P[0]}]
+# set_property PACKAGE_PIN AE37 [get_ports {GBTCLK_M2C_N[0]}]
+# set_property PACKAGE_PIN AA36 [get_ports {GBTCLK_M2C_P[1]}]
+# set_property PACKAGE_PIN AA37 [get_ports {GBTCLK_M2C_N[1]}]
+
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y4_p [get_ports {GBTCLK_M2C_P[0]}]
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y7_p [get_ports {GBTCLK_M2C_P[1]}]
+
+# # False path constraints
+# # ----------------------------------------------------------------------------------------------------------------------
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]
+
+#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iACLK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CFG_CLK_IBUF_inst/O]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iGPUCLK]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iMCLK]
+
+set_property PULLUP true [get_ports QSPI_D0]
+set_property PULLUP true [get_ports QSPI_D1]
+set_property PULLUP true [get_ports QSPI_D2]
+set_property PULLUP true [get_ports QSPI_D3]
+
+# set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+# set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports "c0_ddr4_bg[0]"]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
+set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
+set_property CONFIG_MODE S_SELECTMAP [current_design]
+
+set_property PACKAGE_PIN AR26 [get_ports NRST]
+set_property PACKAGE_PIN AR27 [get_ports {P0[0]}]
+set_property PACKAGE_PIN AW29 [get_ports {P0[10]}]
+set_property PACKAGE_PIN BA25 [get_ports {P0[11]}]
+set_property PACKAGE_PIN BB25 [get_ports {P0[12]}]
+set_property PACKAGE_PIN AY28 [get_ports {P0[13]}]
+set_property PACKAGE_PIN BA28 [get_ports {P0[14]}]
+set_property PACKAGE_PIN AY26 [get_ports {P0[15]}]
+set_property PACKAGE_PIN AR28 [get_ports {P0[1]}]
+set_property PACKAGE_PIN AT28 [get_ports {P0[2]}]
+set_property PACKAGE_PIN AU25 [get_ports {P0[3]}]
+set_property PACKAGE_PIN AU26 [get_ports {P0[4]}]
+set_property PACKAGE_PIN AU27 [get_ports {P0[5]}]
+set_property PACKAGE_PIN AV28 [get_ports {P0[6]}]
+set_property PACKAGE_PIN BB26 [get_ports {P0[7]}]
+set_property PACKAGE_PIN BB27 [get_ports {P0[8]}]
+set_property PACKAGE_PIN AW28 [get_ports {P0[9]}]
+set_property PACKAGE_PIN AW26 [get_ports {P1[0]}]
+set_property PACKAGE_PIN AY21 [get_ports {P1[10]}]
+set_property PACKAGE_PIN AY22 [get_ports {P1[11]}]
+set_property PACKAGE_PIN BA22 [get_ports {P1[12]}]
+set_property PACKAGE_PIN AT22 [get_ports {P1[13]}]
+set_property PACKAGE_PIN AT23 [get_ports {P1[14]}]
+set_property PACKAGE_PIN AR25 [get_ports {P1[15]}]
+set_property PACKAGE_PIN AY27 [get_ports {P1[1]}]
+set_property PACKAGE_PIN AW23 [get_ports {P1[2]}]
+set_property PACKAGE_PIN AY23 [get_ports {P1[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {P1[4]}]
+set_property PACKAGE_PIN BB21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN BB22 [get_ports {P1[6]}]
+set_property PACKAGE_PIN BA23 [get_ports {P1[7]}]
+set_property PACKAGE_PIN BA24 [get_ports {P1[8]}]
+set_property PACKAGE_PIN AW21 [get_ports {P1[9]}]
+set_property PACKAGE_PIN AW24 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN AU22 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN AV23 [get_ports VDD]
+set_property PACKAGE_PIN AT24 [get_ports VDDIO]
+set_property PACKAGE_PIN AT25 [get_ports VSS]
+set_property PACKAGE_PIN AV21 [get_ports VSSIO]
+set_property PACKAGE_PIN AY25 [get_ports XTAL1]
+set_property PACKAGE_PIN AV22 [get_ports XTAL2]
diff --git a/fpga/targets/arm_mps3/fpga_synth.tcl b/fpga/targets/arm_mps3/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b89d747c16fc5a7319b9e0a8f1e0f48df0fafd8
--- /dev/null
+++ b/fpga/targets/arm_mps3/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
diff --git a/fpga/targets/arm_mps3/fpga_timing.xdc b/fpga/targets/arm_mps3/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..78ac5e66193d3180e0df08f400cc924f8f74e8be
--- /dev/null
+++ b/fpga/targets/arm_mps3/fpga_timing.xdc
@@ -0,0 +1,99 @@
+##################################################################################
+## ##
+## Arm MPS3 Rev-C timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks SWCLK]
+
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
+set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
+set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
+
diff --git a/fpga/targets/pynq_z2/design_1.tcl b/fpga/targets/pynq_z2/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e315668f358e9835ae7579d1b495e30e84673413
--- /dev/null
+++ b/fpga/targets/pynq_z2/design_1.tcl
@@ -0,0 +1,644 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:processing_system7:5.5\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {Hamming} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Memory_Type {Single_Port_RAM} \
+ CONFIG.Port_A_Write_Rate {50} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {20.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {20000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {8} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ ] $processing_system7_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+
+ # Create address segments
+ assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/fpga/targets/pynq_z2/design_1_wrapper.v b/fpga/targets/pynq_z2/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/fpga/targets/pynq_z2/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/fpga/targets/pynq_z2/fpga_pinmap.xdc b/fpga/targets/pynq_z2/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5599cd2eec9ca0da4c7b57e21412e609fd7d41de
--- /dev/null
+++ b/fpga/targets/pynq_z2/fpga_pinmap.xdc
@@ -0,0 +1,33 @@
+##################################################################################
+## ##
+## PZ2 PMODA XDC ##
+## ##
+##################################################################################
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+
+set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
diff --git a/fpga/targets/pynq_z2/fpga_synth.tcl b/fpga/targets/pynq_z2/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1a9e44eff2f8e3cc3a24a1c5e1da88ae70f62c90
--- /dev/null
+++ b/fpga/targets/pynq_z2/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
diff --git a/fpga/targets/pynq_z2/fpga_timing.xdc b/fpga/targets/pynq_z2/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/fpga/targets/pynq_z2/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/fpga/targets/pynq_zcu104/design_1.tcl b/fpga/targets/pynq_zcu104/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1c371ce955932e2bb0f599980de721b9bf6feb7f
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/design_1.tcl
@@ -0,0 +1,1154 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {0} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/fpga/targets/pynq_zcu104/design_1_wrapper.v b/fpga/targets/pynq_zcu104/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/fpga/targets/pynq_zcu104/fpga_pinmap.xdc b/fpga/targets/pynq_zcu104/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4a635dde3eeee4ba52cd771abdd9df48b7e59231
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/fpga_pinmap.xdc
@@ -0,0 +1,1031 @@
+##################################################################################
+## ##
+## ZCU104 Rev1.0 Master XDC ##
+## ##
+##################################################################################
+
+#Other net PACKAGE_PIN V17 - SYSMON_DXN Bank 0 - DXN
+#Other net PACKAGE_PIN V18 - SYSMON_DXP Bank 0 - DXP
+#Other net PACKAGE_PIN R17 - SYSMON_AGND Bank 0 - GNDADC
+#Other net PACKAGE_PIN AA12 - 3N5824 Bank 0 - POR_OVERRIDE
+#Other net PACKAGE_PIN AA13 - 3N5822 Bank 0 - PUDC_B
+#Other net PACKAGE_PIN R18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC
+#Other net PACKAGE_PIN U17 - SYSMON_VN_R Bank 0 - VN
+#Other net PACKAGE_PIN T18 - SYSMON_VP_R Bank 0 - VP
+#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - VREFN
+#Other net PACKAGE_PIN U18 - SYSMON_AGND Bank 0 - VREFP
+#set_property PACKAGE_PIN B21 [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property PACKAGE_PIN B20 [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property PACKAGE_PIN A23 [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property PACKAGE_PIN A22 [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property PACKAGE_PIN B19 [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property PACKAGE_PIN B18 [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property PACKAGE_PIN A21 [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property PACKAGE_PIN A18 [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property PACKAGE_PIN B23 [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property PACKAGE_PIN F25 [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property PACKAGE_PIN G26 [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property PACKAGE_PIN G25 [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property PACKAGE_PIN C23 [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property PACKAGE_PIN D22 [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property PACKAGE_PIN D24 [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property PACKAGE_PIN E24 [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property PACKAGE_PIN C22 [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property PACKAGE_PIN C21 [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property PACKAGE_PIN G24 [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property PACKAGE_PIN G23 [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property PACKAGE_PIN F20 [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property PACKAGE_PIN G20 [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property PACKAGE_PIN D21 [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property PACKAGE_PIN D20 [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property PACKAGE_PIN H22 [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property PACKAGE_PIN H21 [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property PACKAGE_PIN D19 [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property PACKAGE_PIN E19 [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property PACKAGE_PIN E20 [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property PACKAGE_PIN H23 [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property PACKAGE_PIN H24 [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property PACKAGE_PIN J24 [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property PACKAGE_PIN H26 [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property PACKAGE_PIN J25 [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property PACKAGE_PIN K23 [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property PACKAGE_PIN K22 [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property PACKAGE_PIN J22 [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property PACKAGE_PIN J21 [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property PACKAGE_PIN K24 [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property PACKAGE_PIN L23 [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property PACKAGE_PIN L22 [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property PACKAGE_PIN L21 [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#Other net PACKAGE_PIN M23 - 5N7631 Bank 28 - VREF_28
+#set_property PACKAGE_PIN A9 [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property PACKAGE_PIN G13 [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property PACKAGE_PIN G11 [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property PACKAGE_PIN H11 [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property PACKAGE_PIN G9 [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property PACKAGE_PIN H9 [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property PACKAGE_PIN D7 [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property PACKAGE_PIN H14 [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property PACKAGE_PIN K13 [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property PACKAGE_PIN L14 [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property PACKAGE_PIN J14 [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property PACKAGE_PIN K14 [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property PACKAGE_PIN J11 [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property PACKAGE_PIN K12 [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property PACKAGE_PIN L11 [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property PACKAGE_PIN L12 [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#Other net PACKAGE_PIN J12 - 4N9503 Bank 68 - VREF_68
+#set_property PACKAGE_PIN J20 [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property PACKAGE_PIN J19 [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property PACKAGE_PIN G16 [get_ports "FMC_LPC_LA09_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67
+#set_property PACKAGE_PIN D14 [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property PACKAGE_PIN D15 [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property PACKAGE_PIN F13 [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property PACKAGE_PIN G14 [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property PACKAGE_PIN E13 [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property PACKAGE_PIN C14 [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property PACKAGE_PIN C12 [get_ports "FMC_LPC_LA14_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67
+#set_property PACKAGE_PIN B13 [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property PACKAGE_PIN B14 [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property PACKAGE_PIN A14 [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property PACKAGE_PIN A15 [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property PACKAGE_PIN B15 [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property PACKAGE_PIN B16 [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property PACKAGE_PIN A16 [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property PACKAGE_PIN A17 [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#Other net PACKAGE_PIN L18 - 7N9719 Bank 67 - VREF_67
+#set_property PACKAGE_PIN AF10 [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property PACKAGE_PIN AC14 [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property PACKAGE_PIN AH8 [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property PACKAGE_PIN AJ12 [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property PACKAGE_PIN AL13 [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property PACKAGE_PIN AM13 [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property PACKAGE_PIN AP8 [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property PACKAGE_PIN AP12 [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#Other net PACKAGE_PIN AB12 - 7N8282 Bank 66 - VREF_66
+#set_property PACKAGE_PIN AE19 [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property PACKAGE_PIN AE22 [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property PACKAGE_PIN AF20 [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property PACKAGE_PIN AH23 [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property PACKAGE_PIN AL21 [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property PACKAGE_PIN AH19 [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property PACKAGE_PIN AM20 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property PACKAGE_PIN AP20 [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#Other net PACKAGE_PIN AB20 - 6N11582 Bank 65 - VREF_65
+#set_property PACKAGE_PIN AA17 [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property PACKAGE_PIN AE17 [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property PACKAGE_PIN AP14 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64
+#set_property PACKAGE_PIN AP15 [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property PACKAGE_PIN AP16 [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property PACKAGE_PIN AN14 [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property PACKAGE_PIN AM14 [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property PACKAGE_PIN AN18 [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property PACKAGE_PIN AM18 [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property PACKAGE_PIN AP13 [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property PACKAGE_PIN AN13 [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property PACKAGE_PIN AP17 [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property PACKAGE_PIN AP18 [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#set_property IOSTANDARD LVCMOSxxn [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#Other net PACKAGE_PIN AG16 - 6N11370 Bank 64 - VREF_64
+#Other net PACKAGE_PIN AD9 - MGT1V2 Bank 224 - MGTAVTTRCAL_R
+#Other net PACKAGE_PIN A24 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0
+#Other net PACKAGE_PIN C24 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1
+#Other net PACKAGE_PIN F26 - 53N7803 Bank 500 - PS_MIO10
+#Other net PACKAGE_PIN B26 - 53N7806 Bank 500 - PS_MIO11
+#Other net PACKAGE_PIN C27 - 53N7809 Bank 500 - PS_MIO12
+#Other net PACKAGE_PIN D27 - 53N7788 Bank 500 - PS_MIO13
+#Other net PACKAGE_PIN A27 - 53N7844 Bank 500 - PS_MIO14
+#Other net PACKAGE_PIN E27 - 53N7842 Bank 500 - PS_MIO15
+#Other net PACKAGE_PIN A28 - MIO16_I2C1_SCL Bank 500 - PS_MIO16
+#Other net PACKAGE_PIN C29 - MIO17_I2C1_SDA Bank 500 - PS_MIO17
+#Other net PACKAGE_PIN F27 - UART0_TXD_MIO18_RXD Bank 500 - PS_MIO18
+#Other net PACKAGE_PIN B28 - UART0_RXD_MIO19_TXD Bank 500 - PS_MIO19
+#Other net PACKAGE_PIN B24 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2
+#Other net PACKAGE_PIN E29 - UART1_RXD_MIO20_TXD Bank 500 - PS_MIO20
+#Other net PACKAGE_PIN C28 - UART1_TXD_MIO21_RXD Bank 500 - PS_MIO21
+#Other net PACKAGE_PIN F28 - 53N7824 Bank 500 - PS_MIO22
+#Other net PACKAGE_PIN B29 - 53N7822 Bank 500 - PS_MIO23
+#Other net PACKAGE_PIN E28 - MIO24_CAN_TX Bank 500 - PS_MIO24
+#Other net PACKAGE_PIN D29 - MIO25_CAN_RX Bank 500 - PS_MIO25
+#Other net PACKAGE_PIN E25 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3
+#Other net PACKAGE_PIN A25 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4
+#Other net PACKAGE_PIN D25 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5
+#Other net PACKAGE_PIN A26 - 53N6816 Bank 500 - PS_MIO6
+#Other net PACKAGE_PIN B25 - 53N7794 Bank 500 - PS_MIO7
+#Other net PACKAGE_PIN D26 - 53N7797 Bank 500 - PS_MIO8
+#Other net PACKAGE_PIN C26 - 53N7800 Bank 500 - PS_MIO9
+#Other net PACKAGE_PIN AA25 - PS_SYSMON_AVCC Bank 500 - VCC_PSADC
+#Other net PACKAGE_PIN AA24 - PS_SYSMON_AGND Bank 500 - GND_PSADC
+#Other net PACKAGE_PIN A29 - 53N7791 Bank 501 - PS_MIO26
+#Other net PACKAGE_PIN A30 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27
+#Other net PACKAGE_PIN A31 - MIO28_DP_HPD Bank 501 - PS_MIO28
+#Other net PACKAGE_PIN A32 - MIO29_DP_OE Bank 501 - PS_MIO29
+#Other net PACKAGE_PIN A33 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30
+#Other net PACKAGE_PIN B30 - 53N7736 Bank 501 - PS_MIO31
+#Other net PACKAGE_PIN B31 - 53N7739 Bank 501 - PS_MIO32
+#Other net PACKAGE_PIN B33 - 53N7742 Bank 501 - PS_MIO33
+#Other net PACKAGE_PIN B34 - 53N7745 Bank 501 - PS_MIO34
+#Other net PACKAGE_PIN C31 - 53N7748 Bank 501 - PS_MIO35
+#Other net PACKAGE_PIN C32 - 53N7751 Bank 501 - PS_MIO36
+#Other net PACKAGE_PIN C33 - 53N7754 Bank 501 - PS_MIO37
+#Other net PACKAGE_PIN C34 - 53N7768 Bank 501 - PS_MIO38
+#Other net PACKAGE_PIN D30 - 53N7771 Bank 501 - PS_MIO39
+#Other net PACKAGE_PIN D31 - 53N7773 Bank 501 - PS_MIO40
+#Other net PACKAGE_PIN D32 - 53N7775 Bank 501 - PS_MIO41
+#Other net PACKAGE_PIN D34 - 53N7777 Bank 501 - PS_MIO42
+#Other net PACKAGE_PIN E30 - 53N6798 Bank 501 - PS_MIO43
+#Other net PACKAGE_PIN E32 - 53N7783 Bank 501 - PS_MIO44
+#Other net PACKAGE_PIN E33 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45
+#Other net PACKAGE_PIN E34 - MIO46_SDIO_DAT0_R Bank 501 - PS_MIO46
+#Other net PACKAGE_PIN F30 - MIO47_SDIO_DAT1_R Bank 501 - PS_MIO47
+#Other net PACKAGE_PIN F31 - MIO48_SDIO_DAT2_R Bank 501 - PS_MIO48
+#Other net PACKAGE_PIN F32 - MIO49_SDIO_DAT3_R Bank 501 - PS_MIO49
+#Other net PACKAGE_PIN F33 - MIO50_SDIO_CMD_R Bank 501 - PS_MIO50
+#Other net PACKAGE_PIN F34 - MIO51_SDIO_CLK_R Bank 501 - PS_MIO51
+#Other net PACKAGE_PIN G29 - MIO52_USB_CLK Bank 502 - PS_MIO52
+#Other net PACKAGE_PIN G30 - MIO53_USB_DIR Bank 502 - PS_MIO53
+#Other net PACKAGE_PIN G31 - MIO54_USB_DATA2_R Bank 502 - PS_MIO54
+#Other net PACKAGE_PIN G33 - MIO55_USB_NXT Bank 502 - PS_MIO55
+#Other net PACKAGE_PIN G34 - MIO56_USB_DATA0_R Bank 502 - PS_MIO56
+#Other net PACKAGE_PIN H29 - MIO57_USB_DATA1_R Bank 502 - PS_MIO57
+#Other net PACKAGE_PIN H31 - MIO58_USB_STP_R Bank 502 - PS_MIO58
+#Other net PACKAGE_PIN H32 - MIO59_USB_DATA3_R Bank 502 - PS_MIO59
+#Other net PACKAGE_PIN H33 - MIO60_USB_DATA4_R Bank 502 - PS_MIO60
+#Other net PACKAGE_PIN H34 - MIO61_USB_DATA5_R Bank 502 - PS_MIO61
+#Other net PACKAGE_PIN J29 - MIO62_USB_DATA6_R Bank 502 - PS_MIO62
+#Other net PACKAGE_PIN J30 - MIO63_USB_DATA7_R Bank 502 - PS_MIO63
+#Other net PACKAGE_PIN J31 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64
+#Other net PACKAGE_PIN J32 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65
+#Other net PACKAGE_PIN J34 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66
+#Other net PACKAGE_PIN K28 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67
+#Other net PACKAGE_PIN K29 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68
+#Other net PACKAGE_PIN K30 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69
+#Other net PACKAGE_PIN K31 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70
+#Other net PACKAGE_PIN K32 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71
+#Other net PACKAGE_PIN K33 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72
+#Other net PACKAGE_PIN K34 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73
+#Other net PACKAGE_PIN L29 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74
+#Other net PACKAGE_PIN L30 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75
+#Other net PACKAGE_PIN L33 - MIO76_ENET_MDC Bank 502 - PS_MIO76
+#Other net PACKAGE_PIN L34 - MIO77_ENET_MDIO Bank 502 - PS_MIO77
+#Other net PACKAGE_PIN N24 - PS_DONE Bank 503 - PS_DONE
+#Other net PACKAGE_PIN T25 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT
+#Other net PACKAGE_PIN R25 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS
+#Other net PACKAGE_PIN P24 - PS_INIT_B Bank 503 - PS_INIT_B
+#Other net PACKAGE_PIN K27 - FPGA_TCK Bank 503 - PS_JTAG_TCK
+#Other net PACKAGE_PIN J27 - FPGA_TDI Bank 503 - PS_JTAG_TDI
+#Other net PACKAGE_PIN G28 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO
+#Other net PACKAGE_PIN H28 - FPGA_TMS Bank 503 - PS_JTAG_TMS
+#Other net PACKAGE_PIN H27 - PS_MODE0 Bank 503 - PS_MODE0
+#Other net PACKAGE_PIN J26 - PS_MODE1 Bank 503 - PS_MODE1
+#Other net PACKAGE_PIN K26 - PS_MODE2 Bank 503 - PS_MODE2
+#Other net PACKAGE_PIN K25 - PS_MODE3 Bank 503 - PS_MODE3
+#Other net PACKAGE_PIN M25 - PS_PADI Bank 503 - PS_PADI
+#Other net PACKAGE_PIN L25 - PS_PADO Bank 503 - PS_PADO
+#Other net PACKAGE_PIN M24 - PS_POR_B Bank 503 - PS_POR_B
+#Other net PACKAGE_PIN T24 - PS_PROG_B Bank 503 - PS_PROG_B
+#Other net PACKAGE_PIN R24 - PS_REF_CLK Bank 503 - PS_REF_CLK
+#Other net PACKAGE_PIN P25 - PS_SRST_B Bank 503 - PS_SRST_B
+#Other net PACKAGE_PIN AN34 - DDR4_A0 Bank 504 - PS_DDR_A0
+#Other net PACKAGE_PIN AM34 - DDR4_A1 Bank 504 - PS_DDR_A1
+#Other net PACKAGE_PIN AG31 - DDR4_A10 Bank 504 - PS_DDR_A10
+#Other net PACKAGE_PIN AF31 - DDR4_A11 Bank 504 - PS_DDR_A11
+#Other net PACKAGE_PIN AG30 - DDR4_A12 Bank 504 - PS_DDR_A12
+#Other net PACKAGE_PIN AF30 - DDR4_A13 Bank 504 - PS_DDR_A13
+#Other net PACKAGE_PIN AG29 - DDR4_A14_WE_B Bank 504 - PS_DDR_A14
+#Other net PACKAGE_PIN AG28 - DDR4_A15_CAS_B Bank 504 - PS_DDR_A15
+#Other net PACKAGE_PIN AF28 - DDR4_A16_RAS_B Bank 504 - PS_DDR_A16
+#Other net PACKAGE_PIN AF26 - 68N6692 Bank 504 - PS_DDR_A17
+#Other net PACKAGE_PIN AM33 - DDR4_A2 Bank 504 - PS_DDR_A2
+#Other net PACKAGE_PIN AL34 - DDR4_A3 Bank 504 - PS_DDR_A3
+#Other net PACKAGE_PIN AL33 - DDR4_A4 Bank 504 - PS_DDR_A4
+#Other net PACKAGE_PIN AK33 - DDR4_A5 Bank 504 - PS_DDR_A5
+#Other net PACKAGE_PIN AK30 - DDR4_A6 Bank 504 - PS_DDR_A6
+#Other net PACKAGE_PIN AJ30 - DDR4_A7 Bank 504 - PS_DDR_A7
+#Other net PACKAGE_PIN AJ31 - DDR4_A8 Bank 504 - PS_DDR_A8
+#Other net PACKAGE_PIN AH31 - DDR4_A9 Bank 504 - PS_DDR_A9
+#Other net PACKAGE_PIN AE25 - DDR4_ACT_B Bank 504 - PS_DDR_ACT_N
+#Other net PACKAGE_PIN AB26 - DDR4_ALERT_B Bank 504 - PS_DDR_ALERT_N
+#Other net PACKAGE_PIN AE27 - DDR4_BA0 Bank 504 - PS_DDR_BA0
+#Other net PACKAGE_PIN AE28 - DDR4_BA1 Bank 504 - PS_DDR_BA1
+#Other net PACKAGE_PIN AD27 - DDR4_BG0 Bank 504 - PS_DDR_BG0
+#Other net PACKAGE_PIN AF27 - 68N7393 Bank 504 - PS_DDR_BG1
+#Other net PACKAGE_PIN AL31 - DDR4_CK_T Bank 504 - PS_DDR_CK0
+#Other net PACKAGE_PIN AL30 - 68N7399 Bank 504 - PS_DDR_CK1
+#Other net PACKAGE_PIN AN33 - DDR4_CKE Bank 504 - PS_DDR_CKE0
+#Other net PACKAGE_PIN AH32 - 68N7405 Bank 504 - PS_DDR_CKE1
+#Other net PACKAGE_PIN AN32 - DDR4_CK_C Bank 504 - PS_DDR_CK_N0
+#Other net PACKAGE_PIN AL32 - 68N7402 Bank 504 - PS_DDR_CK_N1
+#Other net PACKAGE_PIN AP33 - DDR4_CS_B Bank 504 - PS_DDR_CS_N0
+#Other net PACKAGE_PIN AK32 - 68N7396 Bank 504 - PS_DDR_CS_N1
+#Other net PACKAGE_PIN AN24 - DDR4_DM0 Bank 504 - PS_DDR_DM0
+#Other net PACKAGE_PIN AM29 - DDR4_DM1 Bank 504 - PS_DDR_DM1
+#Other net PACKAGE_PIN AH24 - DDR4_DM2 Bank 504 - PS_DDR_DM2
+#Other net PACKAGE_PIN AJ29 - DDR4_DM3 Bank 504 - PS_DDR_DM3
+#Other net PACKAGE_PIN AD29 - DDR4_DM4 Bank 504 - PS_DDR_DM4
+#Other net PACKAGE_PIN Y29 - DDR4_DM5 Bank 504 - PS_DDR_DM5
+#Other net PACKAGE_PIN AC32 - DDR4_DM6 Bank 504 - PS_DDR_DM6
+#Other net PACKAGE_PIN Y32 - DDR4_DM7 Bank 504 - PS_DDR_DM7
+#Other net PACKAGE_PIN AF34 - 68N7353 Bank 504 - PS_DDR_DM8
+#Other net PACKAGE_PIN AP27 - DDR4_DQ0 Bank 504 - PS_DDR_DQ0
+#Other net PACKAGE_PIN AP25 - DDR4_DQ1 Bank 504 - PS_DDR_DQ1
+#Other net PACKAGE_PIN AP29 - DDR4_DQ10 Bank 504 - PS_DDR_DQ10
+#Other net PACKAGE_PIN AP28 - DDR4_DQ11 Bank 504 - PS_DDR_DQ11
+#Other net PACKAGE_PIN AM31 - DDR4_DQ12 Bank 504 - PS_DDR_DQ12
+#Other net PACKAGE_PIN AP31 - DDR4_DQ13 Bank 504 - PS_DDR_DQ13
+#Other net PACKAGE_PIN AN31 - DDR4_DQ14 Bank 504 - PS_DDR_DQ14
+#Other net PACKAGE_PIN AM30 - DDR4_DQ15 Bank 504 - PS_DDR_DQ15
+#Other net PACKAGE_PIN AF25 - DDR4_DQ16 Bank 504 - PS_DDR_DQ16
+#Other net PACKAGE_PIN AG25 - DDR4_DQ17 Bank 504 - PS_DDR_DQ17
+#Other net PACKAGE_PIN AG26 - DDR4_DQ18 Bank 504 - PS_DDR_DQ18
+#Other net PACKAGE_PIN AJ25 - DDR4_DQ19 Bank 504 - PS_DDR_DQ19
+#Other net PACKAGE_PIN AP26 - DDR4_DQ2 Bank 504 - PS_DDR_DQ2
+#Other net PACKAGE_PIN AG24 - DDR4_DQ20 Bank 504 - PS_DDR_DQ20
+#Other net PACKAGE_PIN AK25 - DDR4_DQ21 Bank 504 - PS_DDR_DQ21
+#Other net PACKAGE_PIN AJ24 - DDR4_DQ22 Bank 504 - PS_DDR_DQ22
+#Other net PACKAGE_PIN AK24 - DDR4_DQ23 Bank 504 - PS_DDR_DQ23
+#Other net PACKAGE_PIN AH28 - DDR4_DQ24 Bank 504 - PS_DDR_DQ24
+#Other net PACKAGE_PIN AH27 - DDR4_DQ25 Bank 504 - PS_DDR_DQ25
+#Other net PACKAGE_PIN AJ27 - DDR4_DQ26 Bank 504 - PS_DDR_DQ26
+#Other net PACKAGE_PIN AK27 - DDR4_DQ27 Bank 504 - PS_DDR_DQ27
+#Other net PACKAGE_PIN AL26 - DDR4_DQ28 Bank 504 - PS_DDR_DQ28
+#Other net PACKAGE_PIN AL27 - DDR4_DQ29 Bank 504 - PS_DDR_DQ29
+#Other net PACKAGE_PIN AM26 - DDR4_DQ3 Bank 504 - PS_DDR_DQ3
+#Other net PACKAGE_PIN AH29 - DDR4_DQ30 Bank 504 - PS_DDR_DQ30
+#Other net PACKAGE_PIN AL28 - DDR4_DQ31 Bank 504 - PS_DDR_DQ31
+#Other net PACKAGE_PIN AB29 - DDR4_DQ32 Bank 504 - PS_DDR_DQ32
+#Other net PACKAGE_PIN AB30 - DDR4_DQ33 Bank 504 - PS_DDR_DQ33
+#Other net PACKAGE_PIN AC29 - DDR4_DQ34 Bank 504 - PS_DDR_DQ34
+#Other net PACKAGE_PIN AD32 - DDR4_DQ35 Bank 504 - PS_DDR_DQ35
+#Other net PACKAGE_PIN AC31 - DDR4_DQ36 Bank 504 - PS_DDR_DQ36
+#Other net PACKAGE_PIN AE30 - DDR4_DQ37 Bank 504 - PS_DDR_DQ37
+#Other net PACKAGE_PIN AC28 - DDR4_DQ38 Bank 504 - PS_DDR_DQ38
+#Other net PACKAGE_PIN AE29 - DDR4_DQ39 Bank 504 - PS_DDR_DQ39
+#Other net PACKAGE_PIN AP24 - DDR4_DQ4 Bank 504 - PS_DDR_DQ4
+#Other net PACKAGE_PIN AC27 - DDR4_DQ40 Bank 504 - PS_DDR_DQ40
+#Other net PACKAGE_PIN AA27 - DDR4_DQ41 Bank 504 - PS_DDR_DQ41
+#Other net PACKAGE_PIN AA28 - DDR4_DQ42 Bank 504 - PS_DDR_DQ42
+#Other net PACKAGE_PIN AB28 - DDR4_DQ43 Bank 504 - PS_DDR_DQ43
+#Other net PACKAGE_PIN W27 - DDR4_DQ44 Bank 504 - PS_DDR_DQ44
+#Other net PACKAGE_PIN W29 - DDR4_DQ45 Bank 504 - PS_DDR_DQ45
+#Other net PACKAGE_PIN W28 - DDR4_DQ46 Bank 504 - PS_DDR_DQ46
+#Other net PACKAGE_PIN V27 - DDR4_DQ47 Bank 504 - PS_DDR_DQ47
+#Other net PACKAGE_PIN AA32 - DDR4_DQ48 Bank 504 - PS_DDR_DQ48
+#Other net PACKAGE_PIN AA33 - DDR4_DQ49 Bank 504 - PS_DDR_DQ49
+#Other net PACKAGE_PIN AL25 - DDR4_DQ5 Bank 504 - PS_DDR_DQ5
+#Other net PACKAGE_PIN AA34 - DDR4_DQ50 Bank 504 - PS_DDR_DQ50
+#Other net PACKAGE_PIN AE34 - DDR4_DQ51 Bank 504 - PS_DDR_DQ51
+#Other net PACKAGE_PIN AD34 - DDR4_DQ52 Bank 504 - PS_DDR_DQ52
+#Other net PACKAGE_PIN AB31 - DDR4_DQ53 Bank 504 - PS_DDR_DQ53
+#Other net PACKAGE_PIN AC34 - DDR4_DQ54 Bank 504 - PS_DDR_DQ54
+#Other net PACKAGE_PIN AC33 - DDR4_DQ55 Bank 504 - PS_DDR_DQ55
+#Other net PACKAGE_PIN AA30 - DDR4_DQ56 Bank 504 - PS_DDR_DQ56
+#Other net PACKAGE_PIN Y30 - DDR4_DQ57 Bank 504 - PS_DDR_DQ57
+#Other net PACKAGE_PIN AA31 - DDR4_DQ58 Bank 504 - PS_DDR_DQ58
+#Other net PACKAGE_PIN W30 - DDR4_DQ59 Bank 504 - PS_DDR_DQ59
+#Other net PACKAGE_PIN AM25 - DDR4_DQ6 Bank 504 - PS_DDR_DQ6
+#Other net PACKAGE_PIN Y33 - DDR4_DQ60 Bank 504 - PS_DDR_DQ60
+#Other net PACKAGE_PIN W33 - DDR4_DQ61 Bank 504 - PS_DDR_DQ61
+#Other net PACKAGE_PIN W34 - DDR4_DQ62 Bank 504 - PS_DDR_DQ62
+#Other net PACKAGE_PIN Y34 - DDR4_DQ63 Bank 504 - PS_DDR_DQ63
+#Other net PACKAGE_PIN AF32 - 68N7356 Bank 504 - PS_DDR_DQ64
+#Other net PACKAGE_PIN AE32 - 68N7359 Bank 504 - PS_DDR_DQ65
+#Other net PACKAGE_PIN AH33 - 68N7362 Bank 504 - PS_DDR_DQ66
+#Other net PACKAGE_PIN AE33 - 68N7364 Bank 504 - PS_DDR_DQ67
+#Other net PACKAGE_PIN AF33 - 68N7368 Bank 504 - PS_DDR_DQ68
+#Other net PACKAGE_PIN AH34 - 68N7370 Bank 504 - PS_DDR_DQ69
+#Other net PACKAGE_PIN AM24 - DDR4_DQ7 Bank 504 - PS_DDR_DQ7
+#Other net PACKAGE_PIN AJ34 - 68N7374 Bank 504 - PS_DDR_DQ70
+#Other net PACKAGE_PIN AK34 - 68N7376 Bank 504 - PS_DDR_DQ71
+#Other net PACKAGE_PIN AM28 - DDR4_DQ8 Bank 504 - PS_DDR_DQ8
+#Other net PACKAGE_PIN AN28 - DDR4_DQ9 Bank 504 - PS_DDR_DQ9
+#Other net PACKAGE_PIN AN27 - DDR4_DQS0_C Bank 504 - PS_DDR_DQS_N0
+#Other net PACKAGE_PIN AP30 - DDR4_DQS1_C Bank 504 - PS_DDR_DQS_N1
+#Other net PACKAGE_PIN AJ26 - DDR4_DQS2_C Bank 504 - PS_DDR_DQS_N2
+#Other net PACKAGE_PIN AK29 - DDR4_DQS3_C Bank 504 - PS_DDR_DQS_N3
+#Other net PACKAGE_PIN AD31 - DDR4_DQS4_C Bank 504 - PS_DDR_DQS_N4
+#Other net PACKAGE_PIN Y28 - DDR4_DQS5_C Bank 504 - PS_DDR_DQS_N5
+#Other net PACKAGE_PIN AB34 - DDR4_DQS6_C Bank 504 - PS_DDR_DQS_N6
+#Other net PACKAGE_PIN W32 - DDR4_DQS7_C Bank 504 - PS_DDR_DQS_N7
+#Other net PACKAGE_PIN AG34 - 68N7350 Bank 504 - PS_DDR_DQS_N8
+#Other net PACKAGE_PIN AN26 - DDR4_DQS0_T Bank 504 - PS_DDR_DQS_P0
+#Other net PACKAGE_PIN AN29 - DDR4_DQS1_T Bank 504 - PS_DDR_DQS_P1
+#Other net PACKAGE_PIN AH26 - DDR4_DQS2_T Bank 504 - PS_DDR_DQS_P2
+#Other net PACKAGE_PIN AK28 - DDR4_DQS3_T Bank 504 - PS_DDR_DQS_P3
+#Other net PACKAGE_PIN AD30 - DDR4_DQS4_T Bank 504 - PS_DDR_DQS_P4
+#Other net PACKAGE_PIN Y27 - DDR4_DQS5_T Bank 504 - PS_DDR_DQS_P5
+#Other net PACKAGE_PIN AB33 - DDR4_DQS6_T Bank 504 - PS_DDR_DQS_P6
+#Other net PACKAGE_PIN W31 - DDR4_DQS7_T Bank 504 - PS_DDR_DQS_P7
+#Other net PACKAGE_PIN AG33 - 68N7347 Bank 504 - PS_DDR_DQS_P8
+#Other net PACKAGE_PIN AP32 - DDR4_ODT Bank 504 - PS_DDR_ODT0
+#Other net PACKAGE_PIN AJ32 - 68N7408 Bank 504 - PS_DDR_ODT1
+#Other net PACKAGE_PIN AA26 - DDR4_PAR Bank 504 - PS_DDR_PARITY
+#Other net PACKAGE_PIN AD26 - DDR4_RESET_B Bank 504 - PS_DDR_RAM_RST_N
+#Other net PACKAGE_PIN AC26 - SODIMM_ZQ Bank 504 - PS_DDR_ZQ
+#Other net PACKAGE_PIN U34 - 69N6524 Bank 505 - PS_MGTRRXN0_505
+#Other net PACKAGE_PIN T32 - 69N6530 Bank 505 - PS_MGTRRXN1_505
+#Other net PACKAGE_PIN R34 - GT2_USB0_RX_N Bank 505 - PS_MGTRRXN2_505
+#Other net PACKAGE_PIN N34 - GT3_SATA1_RX_N Bank 505 - PS_MGTRRXN3_505
+#Other net PACKAGE_PIN U33 - 69N6521 Bank 505 - PS_MGTRRXP0_505
+#Other net PACKAGE_PIN T31 - 69N6527 Bank 505 - PS_MGTRRXP1_505
+#Other net PACKAGE_PIN R33 - GT2_USB0_RX_P Bank 505 - PS_MGTRRXP2_505
+#Other net PACKAGE_PIN N33 - GT3_SATA1_RX_P Bank 505 - PS_MGTRRXP3_505
+#Other net PACKAGE_PIN U30 - GT0_DP_TX_N Bank 505 - PS_MGTRTXN0_505
+#Other net PACKAGE_PIN R30 - GT1_DP_TX_N Bank 505 - PS_MGTRTXN1_505
+#Other net PACKAGE_PIN P32 - GT2_USB0_TX_N Bank 505 - PS_MGTRTXN2_505
+#Other net PACKAGE_PIN N30 - GT3_SATA1_TX_N Bank 505 - PS_MGTRTXN3_505
+#Other net PACKAGE_PIN U29 - GT0_DP_TX_P Bank 505 - PS_MGTRTXP0_505
+#Other net PACKAGE_PIN R29 - GT1_DP_TX_P Bank 505 - PS_MGTRTXP1_505
+#Other net PACKAGE_PIN P31 - GT2_USB0_TX_P Bank 505 - PS_MGTRTXP2_505
+#Other net PACKAGE_PIN N29 - GT3_SATA1_TX_P Bank 505 - PS_MGTRTXP3_505
+#Other net PACKAGE_PIN T28 - 69N6536 Bank 505 - PS_MGTREFCLK0N_505
+#Other net PACKAGE_PIN T27 - 69N6533 Bank 505 - PS_MGTREFCLK0P_505
+#Other net PACKAGE_PIN P28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505
+#Other net PACKAGE_PIN P27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505
+#Other net PACKAGE_PIN M28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505
+#Other net PACKAGE_PIN M27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505
+#Other net PACKAGE_PIN M32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505
+#Other net PACKAGE_PIN M31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505
+#Other net PACKAGE_PIN U31 - 69N5804 Bank 505 - PS_MGTRREF_505
+#Other net PACKAGE_PIN AE16 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AH15 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AJ18 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AF19 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AG22 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AK21 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AF9 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AG12 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AK11 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN E21 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN F24 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN H20 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN D13 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN E16 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN H15 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN F9 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN G12 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN K11 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN J8 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN N10 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN D3 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN E6 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN C25 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN D28 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN B32 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN E31 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN H30 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN J33 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN G27 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN N25 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN AE26 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AE31 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG27 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG32 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ28 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ33 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AL29 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN A1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K6 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AC8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN R8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN T10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN U8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN W8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AD6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AF6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AH6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AK6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AM6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AP6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN M6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN P6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN T6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN Y6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN Y10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN N27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN R27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN N31 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN T29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN R23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN U23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN V23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN N22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN T22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN U22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN T12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN V12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN W12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN M15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN T13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN U13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN Y13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y23 - VCC_PSBATT Bank 999 - VCC_PSBATT
+#Other net PACKAGE_PIN U25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN V25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN AA23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB24 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC24 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AA22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN W24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN Y24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN AD21 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD22 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD23 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD24 - VCCINT_VCU Bank 999 - VCCINT_VCU
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
+set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
+set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
+set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
+set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
+set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
+set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
+set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+#set_property PACKAGE_PIN J9 [get_ports PMOD1_0]
+#set_property PACKAGE_PIN K9 [get_ports PMOD1_1]
+#set_property PACKAGE_PIN K8 [get_ports PMOD1_2]
+#set_property PACKAGE_PIN L8 [get_ports PMOD1_3]
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
+
+#set_property PULLUP true [get_ports PMOD1_7]
+#set_property PULLUP true [get_ports PMOD1_6]
+#set_property PULLUP true [get_ports PMOD1_5]
+#set_property PULLUP true [get_ports PMOD1_4]
+#set_property PULLUP true [get_ports PMOD1_3]
+#set_property PULLUP true [get_ports PMOD1_2]
+#set_property PULLUP true [get_ports PMOD1_1]
+#set_property PULLUP true [get_ports PMOD1_0]
+
+
+#PMODA pin0 to FTCLK
+#set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+#set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+#set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+#set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+#set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+#set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+#set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
+# LED1 to P0[1]
+#set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
+# LED2 to P0[2]
+#set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
+# LED3 to P0[3]
+#set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+#set_property PACKAGE_PIN B4 [get_ports NRST]
+
+# CLK125MHz (need dvider)
+#set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN F23 [get_ports XTAL1]
+
+
+## auto mapped - to remap
+#set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
+#set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
+#set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
+#set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
+#set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
+#set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
+#set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
+#set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
+#set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
+#set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
+#set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
+#set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
+#set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
+#set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
+#set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
+#set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
+#set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
+#set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
+#set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
+#set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
+#set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
+#set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
+#set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
+#set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
+#set_property PACKAGE_PIN E2 [get_ports VDD]
+#set_property PACKAGE_PIN A3 [get_ports VDDIO]
+#set_property PACKAGE_PIN A2 [get_ports VSS]
+#set_property PACKAGE_PIN C1 [get_ports VSSIO]
+#set_property PACKAGE_PIN B1 [get_ports XTAL2]
diff --git a/fpga/targets/pynq_zcu104/fpga_synth.tcl b/fpga/targets/pynq_zcu104/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7e6b0c29e7c2584df999ce9a0bc5b3cb502f4185
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top nanosoc_chip -part xczu7ev-ffvc1156-2-e
diff --git a/fpga/targets/pynq_zcu104/fpga_timing.xdc b/fpga/targets/pynq_zcu104/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..fe6eb50301a0e98b47f0d17b9ca18580479e66f7
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports xtal_clk_i]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports swdclk_i]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
index b421555313af15552408367517a88eeee2b8a1b1..400d80b27df1a0afe67d32086bff3398cdfd172b 100644
--- a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -28,7 +28,6 @@ set pynqDir pynq_export/pz104/pynq/overlays/soclabs
# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
#
source scripts/build_mcu_fpga_ip.tcl
-set_property include_dirs " $env(ACCELERATOR_DIR)/src/rtl $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines/ $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines" [current_fileset]
#
# STEP#1: setup design sources and constraints
#
@@ -82,8 +81,7 @@ set_property top design_1_wrapper [current_fileset]
#
# STEP#3: save in Project mode to complete flow
#
-
-save_project_as $project ./$project -exclude_run_results -force -scan_for_includes
+save_project_as $project ./$project -exclude_run_results -force
update_compile_order -fileset sources_1
diff --git a/fpga_imp/scripts/flist_to_tcl.py b/fpga_imp/scripts/flist_to_tcl.py
deleted file mode 100644
index b5d8f4ece5d5cd334509f2a869f1b6d16ef328fb..0000000000000000000000000000000000000000
--- a/fpga_imp/scripts/flist_to_tcl.py
+++ /dev/null
@@ -1,47 +0,0 @@
-import os
-import argparse
-parser = argparse.ArgumentParser(description="Take flist file for verilog simulation and convert to tcl readable",
- formatter_class=argparse.ArgumentDefaultsHelpFormatter)
-parser.add_argument("-i", "--input", help="input flist file")
-parser.add_argument("-o", "--output", help="output tcl file")
-args = parser.parse_args()
-config = vars(args)
-
-
-def readFlist(fname, outfile):
- for line in open(fname):
- li = line.strip()
- if not li.startswith("//"):
- if li.startswith("-f"):
- #Read file and run readFlist
- li = li.replace("-f ","")
- tmp = li.split('/')
- tmp[0]=tmp[0].replace("$","")
- tmp[0]=tmp[0].replace('(','')
- tmp[0]=tmp[0].replace(')','')
- print(tmp)
- envPath = os.environ.get(tmp[0])
- print(envPath)
- tmp.pop(0)
- infile = envPath
- for dir in tmp:
- infile += '/' + dir
- print(infile)
- readFlist(infile,outfile)
- elif li.endswith(".v"):
- output = (line.rstrip()).replace("$","read_verilog $env")
- outfile.write(output+'\n')
- return
-
-
-if not os.path.exists(config["output"]):
- if os.path.exists(config["input"]):
- outfile = open(config["output"], "a")
- readFlist(config["input"],outfile)
- outfile.close()
- else:
- print("ERROR: Input file does not exist")
-else:
- print("ERROR: Output file already exists")
-
-
diff --git a/makefile b/makefile
index 0fc536715699893f2e5937ddd90d1376d37759ed..39a13f6d4f4554fb45dc42cc4606154b8edca433 100644
--- a/makefile
+++ b/makefile
@@ -49,6 +49,7 @@ VERILOG_DIR := $(NANOSOC_SYSTEM_DIR)/verilog
TESTCODES_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/testcodes
# Project System Directory
+FPGA_IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga
PROJ_SYS_DIR := $(SOCLABS_PROJECT_DIR)/system
PROJ_SW_DIR ?= $(PROJ_SYS_DIR)/testcodes
@@ -170,6 +171,17 @@ PARALLEL_TESTS = 4
# Regression Simulation Timeout
TIMEOUT = 5m
+# Name of generated filelist by python script
+TCL_FLIST_DIR := $(FPGA_IMP_DIR)/flist
+TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
+
+# FPGA_Flow
+tcl_flist:
+ @echo building TCL flist
+ @mkdir -p $(TCL_FLIST_DIR)
+ @(cd $(TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) ;)
+
# Create a Directory to Run a Regression in
$(eval REGRESSION_NAME =$(shell date +%Y_%m_%d_%H_%M_%S))
$(eval REGRESSION_DIR = $(SIM_TOP_DIR)/regression_$(REGRESSION_NAME))
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/bd/bd.tcl b/socket/xilinx_lib/ADPcontrol_1.0/bd/bd.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/component.xml b/socket/xilinx_lib/ADPcontrol_1.0/component.xml
new file mode 100755
index 0000000000000000000000000000000000000000..8b1054692e746f6c07edeebdb9718ef729fa8d6f
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/component.xml
@@ -0,0 +1,1425 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>ADPcontrol</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>com_rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>com_tx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>stdio_rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>stdio_tx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb</spirit:name>
+ <spirit:displayName>AHB_M</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite" spirit:version="2.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite_rtl" spirit:version="2.0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="ahb"/>
+ </spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_htrans</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hsize</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hrdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hwrite</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_haddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hmastlock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hburst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hwdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb_hclk</spirit:name>
+ <spirit:displayName>hclk</spirit:displayName>
+ <spirit:description>rising-edge clock</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:description>100000000</spirit:description>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_BUSIF">com_rx:com_tx:stdio_rx:stdio_tx:ahb</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_RESET">ahb_hresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb_hresetn</spirit:name>
+ <spirit:displayName>hresetn</spirit:displayName>
+ <spirit:description>active low reset</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HRESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:addressSpaces>
+ <spirit:addressSpace>
+ <spirit:name>ahb</spirit:name>
+ <spirit:range spirit:format="bitString" spirit:resolve="user">0x100000000</spirit:range>
+ <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+ <spirit:vendorExtensions>
+ <xilinx:addressSpaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="user" xilinx:id="ADDRSPACE_ENABLEMENT.ahb">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:addressSpaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:addressSpace>
+ </spirit:addressSpaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ADPcontrol_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>e4d9de63</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ADPcontrol_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>e4d9de63</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>936ced64</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>16328387</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>ahb_hclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hresetn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tready</spirit:name>
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+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tready</spirit:name>
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+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tdata</spirit:name>
+ <spirit:wire>
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+ <spirit:right spirit:format="long">0</spirit:right>
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+ <spirit:typeName>wire</spirit:typeName>
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+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tvalid</spirit:name>
+ <spirit:wire>
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+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
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+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_tx_tdata</spirit:name>
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+ <spirit:right spirit:format="long">0</spirit:right>
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+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
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+ <spirit:name>stdio_tx_tready</spirit:name>
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+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
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+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..7b8967c18e34a77bb98084ede844e99853f3e47c
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
@@ -0,0 +1,103 @@
+//-----------------------------------------------------------------------------
+// top-level soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+
+ module ADPcontrol_v1_0 #
+ (
+ // Users to add parameters here
+ parameter PROMPT_CHAR = "]"
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Ports of Axi Slave Bus Interface com_rx
+ input wire ahb_hclk,
+ input wire ahb_hresetn,
+
+ output wire com_rx_tready,
+ input wire [7 : 0] com_rx_tdata,
+ input wire com_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface com_tx
+ output wire com_tx_tvalid,
+ output wire [7 : 0] com_tx_tdata,
+ input wire com_tx_tready,
+
+ // Ports of Axi Slave Bus Interface stdio_rx
+ output wire stdio_rx_tready,
+ input wire [7 : 0] stdio_rx_tdata,
+ input wire stdio_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface stdio_tx
+ output wire stdio_tx_tvalid,
+ output wire [7 : 0] stdio_tx_tdata,
+ input wire stdio_tx_tready,
+
+ output wire [7 : 0] gpo8,
+ input wire [7 : 0] gpi8,
+
+ output wire [31:0] ahb_haddr ,
+ output wire [ 2:0] ahb_hburst ,
+ output wire ahb_hmastlock,
+ output wire [ 3:0] ahb_hprot ,
+ output wire [ 2:0] ahb_hsize ,
+ output wire [ 1:0] ahb_htrans ,
+ output wire [31:0] ahb_hwdata ,
+ output wire ahb_hwrite ,
+ input wire [31:0] ahb_hrdata ,
+ input wire ahb_hready ,
+ input wire ahb_hresp
+ );
+
+ // Add user logic here
+
+ADPmanager
+ #(.PROMPT_CHAR (PROMPT_CHAR))
+ ADPmanager(
+ .HCLK (ahb_hclk ),
+ .HRESETn (ahb_hresetn ),
+ .HADDR32_o (ahb_haddr ),
+ .HBURST3_o (ahb_hburst ),
+ .HMASTLOCK_o (ahb_hmastlock ),
+ .HPROT4_o (ahb_hprot ),
+ .HSIZE3_o (ahb_hsize ),
+ .HTRANS2_o (ahb_htrans ),
+ .HWDATA32_o (ahb_hwdata ),
+ .HWRITE_o (ahb_hwrite ),
+ .HRDATA32_i (ahb_hrdata ),
+ .HREADY_i (ahb_hready ),
+ .HRESP_i (ahb_hresp ),
+ .GPO8_o (gpo8 ),
+ .GPI8_i (gpi8 ),
+ .COMRX_TREADY_o(com_rx_tready),
+ .COMRX_TDATA_i(com_rx_tdata),
+ .COMRX_TVALID_i(com_rx_tvalid),
+ .STDRX_TREADY_o(stdio_rx_tready),
+ .STDRX_TDATA_i(stdio_rx_tdata),
+ .STDRX_TVALID_i(stdio_rx_tvalid),
+ .COMTX_TVALID_o(com_tx_tvalid),
+ .COMTX_TDATA_o(com_tx_tdata),
+ .COMTX_TREADY_i(com_tx_tready),
+ .STDTX_TVALID_o(stdio_tx_tvalid),
+ .STDTX_TDATA_o(stdio_tx_tdata),
+ .STDTX_TREADY_i(stdio_tx_tready)
+
+ );
+
+
+endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
new file mode 100755
index 0000000000000000000000000000000000000000..0e980d36757f551bd13414b0bf8f135a4e6bcafc
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_com_rx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
new file mode 100755
index 0000000000000000000000000000000000000000..ba5f03594fc0075bdc58c0535948374580237a28
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_com_tx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
new file mode 100755
index 0000000000000000000000000000000000000000..30f30e3895ada561f258535ea88f9b012142f738
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_stdio_rx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
new file mode 100755
index 0000000000000000000000000000000000000000..8f4af08975c515e65431d6d12dfe5484ac0cac69
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_stdio_tx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/socket/xilinx_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..3abb2fcb7d874d62c253813441c291e06284c7ab
Binary files /dev/null and b/socket/xilinx_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip differ
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/socket/xilinx_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..07c4c8aeabd268a31f2de71e26a8d0f0c2038df9
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
@@ -0,0 +1,102 @@
+//-----------------------------------------------------------------------------
+// top-level soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+ module ADPcontrol_v1_0 #
+ (
+ // Users to add parameters here
+ parameter PROMPT_CHAR = "]"
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Ports of Axi Slave Bus Interface com_rx
+ input wire ahb_hclk,
+ input wire ahb_hresetn,
+
+ output wire com_rx_tready,
+ input wire [7 : 0] com_rx_tdata,
+ input wire com_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface com_tx
+ output wire com_tx_tvalid,
+ output wire [7 : 0] com_tx_tdata,
+ input wire com_tx_tready,
+
+ // Ports of Axi Slave Bus Interface stdio_rx
+ output wire stdio_rx_tready,
+ input wire [7 : 0] stdio_rx_tdata,
+ input wire stdio_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface stdio_tx
+ output wire stdio_tx_tvalid,
+ output wire [7 : 0] stdio_tx_tdata,
+ input wire stdio_tx_tready,
+
+ output wire [7 : 0] gpo8,
+ input wire [7 : 0] gpi8,
+
+ output wire [31:0] ahb_haddr ,
+ output wire [ 2:0] ahb_hburst ,
+ output wire ahb_hmastlock,
+ output wire [ 3:0] ahb_hprot ,
+ output wire [ 2:0] ahb_hsize ,
+ output wire [ 1:0] ahb_htrans ,
+ output wire [31:0] ahb_hwdata ,
+ output wire ahb_hwrite ,
+ input wire [31:0] ahb_hrdata ,
+ input wire ahb_hready ,
+ input wire ahb_hresp
+ );
+
+ // Add user logic here
+
+ADPmanager
+ #(.PROMPT_CHAR (PROMPT_CHAR))
+ ADPmanager(
+ .HCLK (ahb_hclk ),
+ .HRESETn (ahb_hresetn ),
+ .HADDR32_o (ahb_haddr ),
+ .HBURST3_o (ahb_hburst ),
+ .HMASTLOCK_o (ahb_hmastlock ),
+ .HPROT4_o (ahb_hprot ),
+ .HSIZE3_o (ahb_hsize ),
+ .HTRANS2_o (ahb_htrans ),
+ .HWDATA32_o (ahb_hwdata ),
+ .HWRITE_o (ahb_hwrite ),
+ .HRDATA32_i (ahb_hrdata ),
+ .HREADY_i (ahb_hready ),
+ .HRESP_i (ahb_hresp ),
+ .GPO8_o (gpo8 ),
+ .GPI8_i (gpi8 ),
+ .COMRX_TREADY_o(com_rx_tready),
+ .COMRX_TDATA_i(com_rx_tdata),
+ .COMRX_TVALID_i(com_rx_tvalid),
+ .STDRX_TREADY_o(stdio_rx_tready),
+ .STDRX_TDATA_i(stdio_rx_tdata),
+ .STDRX_TVALID_i(stdio_rx_tvalid),
+ .COMTX_TVALID_o(com_tx_tvalid),
+ .COMTX_TDATA_o(com_tx_tdata),
+ .COMTX_TREADY_i(com_tx_tready),
+ .STDTX_TVALID_o(stdio_tx_tvalid),
+ .STDTX_TDATA_o(stdio_tx_tdata),
+ .STDTX_TREADY_i(stdio_tx_tready)
+
+ );
+
+
+endmodule
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/src/ADPmanager.v b/socket/xilinx_lib/ADPcontrol_1.0/src/ADPmanager.v
new file mode 100755
index 0000000000000000000000000000000000000000..5c6ec0be32e8ca76a5537aa727ae65a67208560c
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/src/ADPmanager.v
@@ -0,0 +1,800 @@
+//-----------------------------------------------------------------------------
+// soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//`define ADPBASIC 1
+
+module ADPmanager // AHB initiator interface
+ #(parameter PROMPT_CHAR = "]"
+ )
+ ( input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR32_o,
+ output wire [ 2:0] HBURST3_o,
+ output wire HMASTLOCK_o,
+ output wire [ 3:0] HPROT4_o,
+ output wire [ 2:0] HSIZE3_o,
+ output wire [ 1:0] HTRANS2_o,
+ output wire [31:0] HWDATA32_o,
+ output wire HWRITE_o,
+ input wire [31:0] HRDATA32_i,
+ input wire HREADY_i,
+ input wire HRESP_i,
+// COMIO interface
+ output wire [ 7:0] GPO8_o,
+ input wire [ 7:0] GPI8_i,
+// input wire COM_RXE_i,
+ input wire [ 7:0] COMRX_TDATA_i,
+ input wire COMRX_TVALID_i,
+ output wire COMRX_TREADY_o,
+// input wire COM_TXF_i,
+ output wire [ 7:0] COMTX_TDATA_o,
+ output wire COMTX_TVALID_o,
+ input wire COMTX_TREADY_i,
+// STDIO interface
+// input wire STDOUT_RXE_i,
+ input wire [ 7:0] STDRX_TDATA_i,
+ input wire STDRX_TVALID_i,
+ output wire STDRX_TREADY_o,
+// input wire STDIN_TXF_i
+ output wire [ 7:0] STDTX_TDATA_o,
+ output wire STDTX_TVALID_o,
+ input wire STDTX_TREADY_i
+);
+
+wire COM_RXE_i = !COMRX_TVALID_i;
+wire COM_TXF_i = !COMTX_TREADY_i;
+
+//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o;
+//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o;
+
+
+wire STD_TXF_i = !STDTX_TREADY_i;
+wire STD_RXE_i = !STDRX_TVALID_i;
+
+`ifdef ADPBASIC
+ localparam BANNERHEX = 32'h50c1ab01;
+`else
+ localparam BANNERHEX = 32'h50c1ab03;
+`endif
+
+localparam CMD_bad = 4'b0000;
+localparam CMD_A = 4'b0001; // set Address
+localparam CMD_C = 4'b0010; // Control
+localparam CMD_R = 4'b0011; // Read word, addr++
+localparam CMD_S = 4'b0100; // Status/STDIN
+localparam CMD_W = 4'b0100; // Write word, addr++
+localparam CMD_X = 4'b0101; // eXit
+`ifndef ADPBASIC
+localparam CMD_F = 4'b1000; // Fill (wordocunt) from addr++
+localparam CMD_M = 4'b1001; // set read Mask
+localparam CMD_P = 4'b1010; // Poll hardware (count)
+localparam CMD_U = 4'b1011; // (Binary) Upload (wordocunt) from addr++
+localparam CMD_V = 4'b1100; // match Value
+`endif
+
+
+function FNvalid_adp_entry; // Escape char
+input [7:0] char8;
+ FNvalid_adp_entry = (char8[7:0] == 8'h1b);
+endfunction
+
+function [3:0] FNvalid_cmd;
+input [7:0] char8;
+case (char8[7:0])
+"A": FNvalid_cmd = CMD_A;
+"a": FNvalid_cmd = CMD_A;
+"C": FNvalid_cmd = CMD_C;
+"c": FNvalid_cmd = CMD_C;
+"R": FNvalid_cmd = CMD_R;
+"r": FNvalid_cmd = CMD_R;
+"S": FNvalid_cmd = CMD_S;
+"s": FNvalid_cmd = CMD_S;
+"W": FNvalid_cmd = CMD_W;
+"w": FNvalid_cmd = CMD_W;
+"X": FNvalid_cmd = CMD_X;
+"x": FNvalid_cmd = CMD_X;
+`ifndef ADPBASIC
+"F": FNvalid_cmd = CMD_F;
+"f": FNvalid_cmd = CMD_F;
+"M": FNvalid_cmd = CMD_M;
+"m": FNvalid_cmd = CMD_M;
+"P": FNvalid_cmd = CMD_P;
+"p": FNvalid_cmd = CMD_P;
+"U": FNvalid_cmd = CMD_U;
+"u": FNvalid_cmd = CMD_U;
+"V": FNvalid_cmd = CMD_V;
+"v": FNvalid_cmd = CMD_V;
+`endif
+default:
+ FNvalid_cmd = 0;
+endcase
+endfunction
+
+function FNvalid_space; // space or tab char
+input [7:0] char8;
+ FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09));
+endfunction
+
+function FNnull; // space or tab char
+input [7:0] char8;
+ FNnull = (char8[7:0] == 8'h00);
+endfunction
+
+function FNexit; // EOF
+input [7:0] char8;
+ FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00));
+endfunction
+
+function FNvalid_EOL; // CR or LF
+input [7:0] char8;
+ FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d));
+endfunction
+
+function FNuppercase;
+input [7:0] char8;
+ FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8);
+endfunction
+
+function [63:0] FNBuild_param64_hexdigit;
+input [63:0] param64;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64
+" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64
+"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000};
+"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001};
+"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010};
+"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011};
+"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100};
+"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101};
+"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110};
+"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111};
+"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000};
+"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001};
+"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged
+endcase
+endfunction
+
+function [63:0] FNBuild_param64_byte;
+input [63:0] param64;
+input [7:0] byte;
+ FNBuild_param64_byte = {byte[7:0], param64[63:08]};
+endfunction
+
+function [31:0] FNBuild_param32_hexdigit;
+input [31:0] param32;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32
+" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32
+"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000};
+"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001};
+"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010};
+"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011};
+"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100};
+"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101};
+"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110};
+"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111};
+"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000};
+"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001};
+"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged
+endcase
+endfunction
+
+function [31:0] FNBuild_param32_byte;
+input [31:0] param32;
+input [7:0] byte;
+ FNBuild_param32_byte = {byte[7:0], param32[31:08]};
+endfunction
+
+
+
+function [7:0] FNmap_hex_digit;
+input [3:0] nibble;
+case (nibble[3:0])
+4'b0000: FNmap_hex_digit = "0";
+4'b0001: FNmap_hex_digit = "1";
+4'b0010: FNmap_hex_digit = "2";
+4'b0011: FNmap_hex_digit = "3";
+4'b0100: FNmap_hex_digit = "4";
+4'b0101: FNmap_hex_digit = "5";
+4'b0110: FNmap_hex_digit = "6";
+4'b0111: FNmap_hex_digit = "7";
+4'b1000: FNmap_hex_digit = "8";
+4'b1001: FNmap_hex_digit = "9";
+4'b1010: FNmap_hex_digit = "a";
+4'b1011: FNmap_hex_digit = "b";
+4'b1100: FNmap_hex_digit = "c";
+4'b1101: FNmap_hex_digit = "d";
+4'b1110: FNmap_hex_digit = "e";
+4'b1111: FNmap_hex_digit = "f";
+default: FNmap_hex_digit = "0";
+endcase
+endfunction
+
+
+// as per Vivado synthesis mapping
+`ifdef ADPFSMDESIGN
+localparam ADP_WRITEHEX = 6'b000000 ;
+localparam ADP_WRITEHEXS = 6'b000001 ;
+localparam ADP_WRITEHEX9 = 6'b000010 ;
+localparam ADP_WRITEHEX8 = 6'b000011 ;
+localparam ADP_WRITEHEX7 = 6'b000100 ;
+localparam ADP_WRITEHEX6 = 6'b000101 ;
+localparam ADP_WRITEHEX5 = 6'b000110 ;
+localparam ADP_WRITEHEX4 = 6'b000111 ;
+localparam ADP_WRITEHEX3 = 6'b001000 ;
+localparam ADP_WRITEHEX2 = 6'b001001 ;
+localparam ADP_WRITEHEX1 = 6'b001010 ;
+localparam ADP_WRITEHEX0 = 6'b001011 ;
+localparam ADP_LINEACK = 6'b001100 ;
+localparam ADP_LINEACK2 = 6'b001101 ;
+localparam ADP_PROMPT = 6'b001110 ;
+localparam ADP_IOCHK = 6'b001111 ;
+localparam ADP_STDOUT = 6'b010000 ;
+localparam ADP_STDOUT1 = 6'b010001 ;
+localparam ADP_STDOUT2 = 6'b010010 ;
+localparam ADP_STDOUT3 = 6'b010011 ;
+localparam ADP_RXCMD = 6'b010100 ;
+localparam ADP_RXPARAM = 6'b010101 ;
+localparam ADP_ACTION = 6'b010110 ;
+localparam ADP_SYSCTL = 6'b010111 ;
+localparam ADP_READ = 6'b011000 ;
+localparam ADP_SYSCHK = 6'b011001 ;
+localparam ADP_STDIN = 6'b011010 ;
+localparam ADP_WRITE = 6'b011011 ;
+localparam ADP_EXIT = 6'b011100 ;
+localparam STD_IOCHK = 6'b011101 ;
+localparam STD_RXD1 = 6'b011110 ;
+localparam STD_RXD2 = 6'b011111 ;
+localparam STD_TXD1 = 6'b100000 ;
+localparam STD_TXD2 = 6'b100001 ;
+localparam ADP_UCTRL = 6'b100010 ;
+localparam ADP_UREADB0 = 6'b100011 ;
+localparam ADP_UREADB1 = 6'b100100 ;
+localparam ADP_UREADB2 = 6'b100101 ;
+localparam ADP_UREADB3 = 6'b100110 ;
+localparam ADP_UWRITE = 6'b100111 ;
+localparam ADP_POLL = 6'b101000 ;
+localparam ADP_POLL1 = 6'b101001 ;
+localparam ADP_POLL2 = 6'b101010 ;
+localparam ADP_FCTRL = 6'b101011 ;
+localparam ADP_FWRITE = 6'b101100 ;
+localparam ADP_ECHOCMD = 6'b101101 ;
+localparam ADP_ECHOBUS = 6'b101110 ;
+localparam ADP_UNKNOWN = 6'b101111 ;
+reg [5:0] adp_state ;
+`else
+// one-hot encoded explicitly
+localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000
+localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001
+localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010
+localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011
+localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100
+localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101
+localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110
+localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111
+localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000
+localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001
+localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010
+localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011
+localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001100
+localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b001101
+localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110
+localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111
+localparam ADP_STDOUT = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000
+localparam ADP_STDOUT1 = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010001
+localparam ADP_STDOUT2 = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010010
+localparam ADP_STDOUT3 = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010011
+localparam ADP_RXCMD = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100
+localparam ADP_RXPARAM = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101
+localparam ADP_ACTION = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110
+localparam ADP_SYSCTL = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111
+localparam ADP_READ = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000
+localparam ADP_SYSCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001
+localparam ADP_STDIN = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010
+localparam ADP_WRITE = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011
+localparam ADP_EXIT = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011100
+localparam STD_IOCHK = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011101
+localparam STD_RXD1 = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011110
+localparam STD_RXD2 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b011111
+localparam STD_TXD1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100000
+localparam STD_TXD2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100001
+localparam ADP_UCTRL = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100010
+localparam ADP_UREADB0 = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100011
+localparam ADP_UREADB1 = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100100
+localparam ADP_UREADB2 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100101
+localparam ADP_UREADB3 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100110
+localparam ADP_UWRITE = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b100111
+localparam ADP_POLL = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101000
+localparam ADP_POLL1 = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b101001
+localparam ADP_POLL2 = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b101010
+localparam ADP_FCTRL = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101011
+localparam ADP_FWRITE = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101100
+localparam ADP_ECHOCMD = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101101
+localparam ADP_ECHOBUS = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101110
+localparam ADP_UNKNOWN = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101111
+reg [47:0] adp_state ;
+`endif
+
+reg [31:0] adp_bus_data;
+reg banner ;
+reg com_tx_req ;
+reg [7:0] com_tx_byte ;
+reg com_rx_ack ;
+reg std_tx_req ;
+reg [ 7:0] std_tx_byte;
+reg std_rx_ack ;
+reg adp_bus_req ;
+reg adp_bus_write ;
+reg adp_bus_err ;
+reg [7:0] adp_cmd ;
+reg [32:0] adp_param ;
+reg [31:0] adp_addr ;
+reg adp_addr_inc;
+reg [31:0] adp_sys ;
+
+assign GPO8_o = adp_sys[7:0];
+
+// ADP RX stream
+wire com_rx_req = COMRX_TVALID_i;
+wire [ 7:0] com_rx_byte = COMRX_TDATA_i;
+assign COMRX_TREADY_o = com_rx_ack;
+// ADP TX stream
+wire com_tx_ack = COMTX_TREADY_i;
+assign COMTX_TDATA_o = com_tx_byte;
+assign COMTX_TVALID_o = com_tx_req;
+// STD RX stream (from STDOUT)
+wire std_rx_req = STDRX_TVALID_i;
+wire [ 7:0] std_rx_byte = STDRX_TDATA_i;
+assign STDRX_TREADY_o = std_rx_ack;
+// STD TX stream (to STDIN)
+wire std_tx_ack = STDTX_TREADY_i;
+assign STDTX_TDATA_o = std_tx_byte;
+assign STDTX_TVALID_o = std_tx_req;
+
+//AMBA AHB master as "stream" interface
+reg ahb_dphase;
+wire ahb_aphase = adp_bus_req & !ahb_dphase;
+wire adp_bus_ack = ahb_dphase & HREADY_i;
+// control pipe
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn)
+ ahb_dphase <= 0;
+ else if (HREADY_i)
+ ahb_dphase <= (ahb_aphase);
+
+assign HADDR32_o = adp_addr;
+assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer;
+assign HMASTLOCK_o = 1'b0;
+assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1};
+assign HSIZE3_o[2:0] = {1'b0, 2'b10};
+assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq
+assign HWDATA32_o = adp_bus_data;
+assign HWRITE_o = adp_bus_write;
+
+
+`ifndef ADPBASIC
+reg [31:0] adp_val;
+reg [31:0] adp_mask;
+reg [31:0] adp_poll;
+reg [31:0] adp_count;
+reg adp_count_dec ;
+wire adp_delay_done;
+wire poll2_loop_next;
+`endif
+
+// ADP_control flags in the 'C' control field
+wire adp_disable;
+wire adp_stdin_wait;
+
+// commnon interface handshake terms
+wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o;
+wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i;
+wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o;
+wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i;
+wire adp_bus_done = (adp_bus_req & adp_bus_ack);
+
+// common task to set up for next state
+task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner)
+// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end
+ begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
+endtask
+task ADP_PROMPT_next; // prepare prompt TX
+ begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end
+endtask
+task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end
+endtask
+task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end
+endtask
+
+task ADP_hexdigit_next; // output nibble
+input [3:0] nibble;
+ begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
+endtask
+task ADP_txchar_next; // output char
+input [7:0] byte;
+ begin com_tx_req<= 1; com_tx_byte <= byte; end
+endtask
+
+task com_rx_nxt; com_rx_ack <=1; endtask
+
+function FNcount_down_zero_next; // param about to be zero
+input [31:0] counter;
+ FNcount_down_zero_next = !(|counter[31:1]);
+endfunction
+
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn) begin
+ adp_state <= ADP_WRITEHEX ;
+ adp_bus_data <= BANNERHEX;
+ banner <= 1; // start-up HEX message
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_bus_err <= 0; // default no bus error
+ adp_cmd <= 0;
+ adp_param <= 0;
+ adp_addr <= 0;
+ adp_addr_inc <= 0;
+ adp_bus_write<= 0;
+`ifndef ADPBASIC
+ adp_count <= 0;
+ adp_count_dec<= 0;
+ adp_val <= 0;
+ adp_mask <= 0;
+ adp_sys <= 0;
+`endif
+ end else begin // default states
+ adp_state <= adp_state; // default to hold current state
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++
+ adp_addr_inc <= 0;
+`ifndef ADPBASIC
+ adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param--
+ adp_count_dec<= 0;
+`endif
+ case (adp_state)
+// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>>
+ STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN
+// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
+ else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending
+ STD_TXD1: // get STD out char
+ if (std_rx_done)
+ begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end
+ else std_rx_ack <= 1; // extend
+ STD_TXD2: // output char to ADP channel
+ if (com_tx_done) begin adp_state <= STD_IOCHK; end
+ else com_tx_req <= 1; // extend
+ STD_RXD1: // read rx char and check for ADP entry else STDIN **
+ if (com_rx_done) begin
+ if (FNvalid_adp_entry(com_rx_byte))
+ begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt
+ else if (std_tx_ack)
+ begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end
+ else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked
+ end else com_rx_ack <= 1; // extend
+ STD_RXD2: // get STD in char
+ if (std_tx_done) begin adp_state <= STD_IOCHK; end
+ else std_tx_req <= 1; // extend
+
+// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>>
+ ADP_PROMPT: // transition after reset deassertion
+ if (com_tx_done) begin adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // extend
+
+ ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+ else if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+
+// if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+// else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+//// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+
+// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>>
+ ADP_STDOUT: // output "<"
+ if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end
+ else com_tx_req <= 1; // extend stream request if not ready
+ ADP_STDOUT1: // get STD out char
+ if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end
+ else std_rx_ack <= 1; // else extend
+ ADP_STDOUT2: // output char
+ if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end
+ else com_tx_req <= 1; // else extend
+ ADP_STDOUT3: // output ">"
+ if (com_tx_done) begin if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end else adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // else extend
+
+// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>>
+ ADP_RXCMD: // read and save ADP command
+ if (com_rx_done) begin
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit
+ else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command
+ else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param
+ else begin adp_cmd <= com_rx_byte; adp_param <= 33'h1_00000000; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter
+ end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_RXPARAM: // read and build hex parameter
+ if (com_rx_done) begin // RX byte
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit
+ else if (FNvalid_EOL(com_rx_byte))
+`ifndef ADPBASIC
+ begin adp_count <= adp_param[31:0]; adp_state <= ADP_ACTION; end // parameter complete on EOL
+`else
+ begin adp_state <= ADP_ACTION; end // parameter complete on EOL
+`endif
+ else
+ begin adp_param <= {1'b0,FNBuild_param32_hexdigit(adp_param[31:0], com_rx_byte)}; com_rx_ack <= 1; end // build parameter
+ end
+ else com_rx_ack <= 1;
+
+ ADP_ACTION: // parse command and action with parameter
+ if (FNexit(com_rx_byte))
+ adp_state <= STD_IOCHK;
+ else if (FNvalid_cmd(adp_cmd) == CMD_A)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0, adp_addr}; else adp_addr <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_C) begin
+ if (adp_param[32]) // report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 1) // clear selected bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 2) // set selected bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 3) // overwrite bits in GPO
+ begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else // 4 etc, report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ end
+ else if (FNvalid_cmd(adp_cmd) == CMD_R)
+ begin ADP_BUSREADINC_next(); adp_state <= ADP_READ;
+`ifndef ADPBASIC
+ adp_count_dec <= 1'b1; // optional loop param
+`endif
+ end // no param required
+ else if (FNvalid_cmd(adp_cmd) == CMD_S)
+ begin adp_state <= ADP_SYSCHK; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_W)
+ begin adp_bus_data <= adp_param[31:0]; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_X)
+ begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end
+`ifndef ADPBASIC
+ else if (FNvalid_cmd(adp_cmd) == CMD_U)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_UCTRL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_M)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0,adp_mask}; else adp_mask <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_P)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_V)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0,adp_val}; else adp_val <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_F)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_FCTRL; // non-zero count
+`endif
+ else
+ begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald
+
+// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_WRITE: // perform bus write at current address pointer (and auto increment)
+ if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= HRESP_i; end
+ else begin ADP_BUSWRITEINC_next(); end // extend request
+
+ ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_bus_err <= HRESP_i; ADP_txchar_next("R"); adp_state <= ADP_ECHOBUS; end
+ else begin
+ ADP_BUSREADINC_next();
+`ifndef ADPBASIC
+ adp_count_dec<= 1'b1;
+`endif
+ end // extend request
+
+`ifndef ADPBASIC
+
+// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>>
+ ADP_UCTRL: // set control value
+ begin com_rx_ack <= 1; adp_state <= ADP_UREADB0; end // read next 4 bytes
+ ADP_UREADB0: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_UREADB1; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB1: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_UREADB2; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB2: // read raw binary byte 0
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_UREADB3; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB3: // read raw binary byte 0
+ if (com_rx_done)
+ begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_UWRITE; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_UREADB0; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+
+// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>>
+ ADP_POLL: // set poll value
+ begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end
+ ADP_POLL1: // wait for read data, no addr++
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; adp_bus_err <= adp_bus_err | HRESP_i; end
+ else begin adp_bus_req <= 1; adp_count_dec <=1; end
+ ADP_POLL2:
+ if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= 1'b1; end // timeout
+ else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) begin adp_state <= ADP_ECHOCMD; adp_param <= {1'b0, (adp_param[31:0] - adp_count)}; end // exact match
+ else adp_state <= ADP_POLL;
+
+// >>>>>>>>>>>>>>>> ADP (ZERO) FILL MEMORY >>>>>>>>>>>>>>>>>>>>>>
+ ADP_FCTRL: // set control value
+ begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_FWRITE; end
+ ADP_FWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_FCTRL; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+`endif
+
+ // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_UNKNOWN: // output "?"
+ if (com_tx_done) begin ADP_LINEACK_next(); end
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_EXIT: // exit ADP mode
+ if (com_tx_done) adp_state <= STD_IOCHK;
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_SYSCHK: // check STDIN fifo
+ begin // no upper flags so STDIN char
+ if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
+ else begin adp_bus_err <= 1'b1; adp_state <= ADP_ECHOCMD; end // signal error then echo comand
+ end
+ ADP_STDIN: // push char into STDIN
+ if (std_tx_done) begin adp_bus_data <= {24'b0,adp_param[7:0]}; ADP_txchar_next("S"); adp_state <= ADP_ECHOBUS; end
+ else std_tx_req <= 1; // extend
+
+ ADP_SYSCTL: // read current status - and report in hex
+ begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); adp_state <= ADP_ECHOBUS; end
+
+ ADP_ECHOCMD: // output command and (param) data
+ begin ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param[31:0]; adp_state <= ADP_ECHOBUS; end // output command char
+ ADP_ECHOBUS: // output command space and (bus) data
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
+ else com_tx_req <= 1; // extend
+
+ ADP_WRITEHEX: // output hex word with prefix
+ begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
+
+ ADP_WRITEHEXS:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX9:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX8:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX7: // output hex nibble 7
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX6: // output hex nibble 6
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX5: // output hex nibble 5
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX4: // output hex nibble 4
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX3: // output hex nibble 3
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX2: // output hex nibble 2
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX1: // output hex nibble 1
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack
+ if (com_tx_done) begin
+ adp_bus_err <= 1'b0; // clear sticky bus error flag
+ if (banner) begin ADP_LINEACK_next(); end
+ else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
+ end else com_tx_req <= 1; // extend
+
+ ADP_LINEACK: // write EOLN
+ if (com_tx_done) begin
+ begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end
+ end else com_tx_req <= 1; // extend
+ ADP_LINEACK2: // CR
+ if (com_tx_done) begin
+ if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end
+`ifndef ADPBASIC
+ else if ((FNvalid_cmd(adp_cmd) == CMD_R) & |adp_count) //// non-zero count
+ begin ADP_BUSREADINC_next(); adp_count_dec <= 1'b1; adp_state <= ADP_READ; end //
+`endif
+ else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end
+ end else com_tx_req <= 1; // extend
+ default:
+ begin ADP_txchar_next("#"); adp_state <= ADP_UNKNOWN; end // default error
+ endcase
+ end
+
+endmodule
+
+////AHBLITE_ADPMASTER instancing
+//ADPmaster
+// #(.PROMPT_CHAR ("]"))
+// ADPmaster(
+// .HCLK (ahb_hclk ),
+// .HRESETn (ahb_hrestn ),
+// .HADDR32_o (ahb_haddr ),
+// .HBURST3_o (ahb_hburst ),
+// .HMASTLOCK_o (ahb_hmastlock ),
+// .HPROT4_o (ahb_hprot ),
+// .HSIZE3_o (ahb_hsize ),
+// .HTRANS2_o (ahb_htrans ),
+// .HWDATA32_o (ahb_hwdata ),
+// .HWRITE_o (ahb_hwrite ),
+// .HRDATA32_i (ahb_hrdata ),
+// .HREADY_i (ahb_hready ),
+// .HRESP_i (ahb_hresp ),
+
+// .COMRX_TREADY_o(com_rx_tready),
+// .COMRX_TDATA_i(com_rx_tdata),
+// .COMRX_TVALID_i(com_rx_tvalid),
+// .STDRX_TREADY_o(std_rx_tready),
+// .STDRX_TDATA_i(std_rx_tdata),
+// .STDRX_TVALID_i(std_rx_tvalid),
+// .COMTX_TVALID_o(com_tx_tvalid),
+// .COMTX_TDATA_o(com_tx_tdata),
+// .COMTX_TREADY_i(com_tx_tready),
+// .STDTX_TVALID_o(std_tx_tvalid),
+// .STDTX_TDATA_o(std_tx_tdata),
+// .STDTX_TREADY_i(std_tx_tready)
+
+// );
diff --git a/socket/xilinx_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/socket/xilinx_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7b1f3777d50c30180f5ec02a105f6d4280b0d604
--- /dev/null
+++ b/socket/xilinx_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
@@ -0,0 +1,24 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+proc update_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to update PROMPT_CHAR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to validate PROMPT_CHAR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.PROMPT_CHAR { MODELPARAM_VALUE.PROMPT_CHAR PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.PROMPT_CHAR}] ${MODELPARAM_VALUE.PROMPT_CHAR}
+}
+
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/bd/bd.tcl b/socket/xilinx_lib/axi_stream_io_1.0/bd/bd.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/component.xml b/socket/xilinx_lib/axi_stream_io_1.0/component.xml
new file mode 100755
index 0000000000000000000000000000000000000000..5696e415cb8e30efb4743373a5ca6747614422b3
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/component.xml
@@ -0,0 +1,1482 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>axi_stream_io</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WREADY</spirit:name>
+ </spirit:physicalPort>
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+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5562313f"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="d6592117"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f0ec23b4"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="7c2aad6e"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd9ec9b5"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="6cced3b9"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
new file mode 100755
index 0000000000000000000000000000000000000000..d7af75e2819376e5c2c39a5f2e0ae96d14f52b63
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER axi_stream_io
+ OPTION supported_peripherals = (axi_stream_io);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = axi_stream_io;
+END DRIVER
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..c3a9cd03e1863921dd4ab5cbc6e020d40ae2757b
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "axi_stream_io" "NUM_INSTANCES" "DEVICE_ID" "C_axi_s_BASEADDR" "C_axi_s_HIGHADDR"
+}
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
new file mode 100755
index 0000000000000000000000000000000000000000..21453f41a1f9f82d13b20509b772556244d9f08d
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling axi_stream_io..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
new file mode 100755
index 0000000000000000000000000000000000000000..c552cbf0e917a961b599672e2ffd4327293d004c
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+
+/************************** Function Definitions ***************************/
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
new file mode 100755
index 0000000000000000000000000000000000000000..294e8516087a45c4aa2229806fe30eb93e47c9b9
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
@@ -0,0 +1,79 @@
+
+#ifndef AXI_STREAM_IO_H
+#define AXI_STREAM_IO_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXI_STREAM_IO_axi_s_SLV_REG0_OFFSET 0
+#define AXI_STREAM_IO_axi_s_SLV_REG1_OFFSET 4
+#define AXI_STREAM_IO_axi_s_SLV_REG2_OFFSET 8
+#define AXI_STREAM_IO_axi_s_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXI_STREAM_IO register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IOdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void AXI_STREAM_IO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXI_STREAM_IO_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXI_STREAM_IO register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IO device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 AXI_STREAM_IO_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXI_STREAM_IO_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IO instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXI_STREAM_IO_H
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
new file mode 100755
index 0000000000000000000000000000000000000000..26bea4d0c70f3d34776b08b13b6c877f2034dea1
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IOinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ AXI_STREAM_IO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( AXI_STREAM_IO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/socket/xilinx_lib/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..6427293a7e3a842cbc0c6c8b2efec11dd4817b08
Binary files /dev/null and b/socket/xilinx_lib/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip differ
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/socket/xilinx_lib/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
new file mode 100755
index 0000000000000000000000000000000000000000..1d30f66be79c030e3aedc8b1e2e5c5095e974158
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
@@ -0,0 +1,418 @@
+
+`timescale 1 ns / 1 ps
+
+ module iostream_v1_0_axi #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXI data bus
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ // Width of S_AXI address bus
+ parameter integer C_S_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ output wire interrupt,
+
+ // Ports of Axi Master Bus Interface tx
+// input wire tx_aclk,
+// input wire tx_aresetn,
+ output wire tx_tvalid,
+ output wire [7 : 0] tx_tdata,
+// output wire [0 : 0] tx_tstrb,
+// output wire tx_tlast,
+ input wire tx_tready,
+
+ // Ports of Axi Slave Bus Interface rx
+// input wire rx_aclk,
+// input wire rx_aresetn,
+ output wire rx_tready,
+ input wire [7 : 0] rx_tdata,
+// input wire [0 : 0] rx_tstrb,
+// input wire rx_tlast,
+ input wire rx_tvalid,
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global Clock Signal
+ input wire S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+ input wire S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+ input wire S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+ output wire S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave)
+ input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.
+ input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+ input wire S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ output wire S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+ output wire [1 : 0] S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+ output wire S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ input wire S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+ input wire S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+ output wire S_AXI_ARREADY,
+ // Read data (issued by slave)
+ output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+ output wire [1 : 0] S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+ output wire S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ input wire S_AXI_RREADY
+ );
+
+ // AXI4LITE signals
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awready;
+ reg axi_wready;
+ reg [1 : 0] axi_bresp;
+ reg axi_bvalid;
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arready;
+ reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+ reg [1 : 0] axi_rresp;
+ reg axi_rvalid;
+
+ // Example-specific design signals
+ // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ // ADDR_LSB is used for addressing 32/64 bit registers/memories
+ // ADDR_LSB = 2 for 32 bits (n downto 2)
+ // ADDR_LSB = 3 for 64 bits (n downto 3)
+ localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+ localparam integer OPT_MEM_ADDR_BITS = 1;
+
+ //----------------------------------------------
+ //-- Signals for user logic register space example
+ //------------------------------------------------
+ //-- Number of Slave Registers 4
+ reg [8:0] tx_reg; // TX data
+ reg [8:0] rx_reg; // RX data
+ reg [7:0] ctrl_reg; // ctrl
+ wire slv_reg_rden;
+ wire slv_reg_wren;
+ reg [7:0] reg_data_out;
+ integer byte_index;
+ reg aw_en;
+
+ wire tx_empty = !tx_reg[8]; // request to transmit
+ wire rx_full = rx_reg[8];
+
+ // I/O Connections assignments
+
+ assign interrupt = ctrl_reg[4] & (tx_empty | rx_full);
+
+ // TX stream interface
+ assign tx_tdata = tx_reg[7:0];
+ assign tx_tvalid = tx_reg[8];
+
+ // RX stream interface
+ assign rx_tready = !rx_reg[8];
+
+ //AXI Slave
+ assign S_AXI_AWREADY = axi_awready;
+ assign S_AXI_WREADY = axi_wready;
+ assign S_AXI_BRESP = axi_bresp;
+ assign S_AXI_BVALID = axi_bvalid;
+ assign S_AXI_ARREADY = axi_arready;
+ assign S_AXI_RDATA = axi_rdata;
+ assign S_AXI_RRESP = axi_rresp;
+ assign S_AXI_RVALID = axi_rvalid;
+ // Implement axi_awready generation
+ // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awready <= 1'b0;
+ aw_en <= 1'b1;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // slave is ready to accept write address when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_awready <= 1'b1;
+ aw_en <= 1'b0;
+ end
+ else if (S_AXI_BREADY && axi_bvalid)
+ begin
+ aw_en <= 1'b1;
+ axi_awready <= 1'b0;
+ end
+ else
+ begin
+ axi_awready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_awaddr latching
+ // This process is used to latch the address when both
+ // S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awaddr <= 0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end
+ end
+ end
+
+ // Implement axi_wready generation
+ // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_wready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+ begin
+ // slave is ready to accept write data when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_wready <= 1'b1;
+ end
+ else
+ begin
+ axi_wready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and write logic generation
+ // The write data is accepted and written to memory mapped registers when
+ // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ // select byte enables of slave registers while writing.
+ // These registers are cleared when reset (active low) is applied.
+ // Slave register write enable is asserted when valid address and data are available
+ // and the slave is ready to accept the write address and write data.
+ assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ rx_reg <= 0;
+ else if ((ctrl_reg[1] == 1'b1)) // RX flush
+ rx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // SW test write
+ rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // Read and clear RX valid pending
+ rx_reg[8] <= 1'b0;
+ else if (rx_tvalid & rx_tready) //(!rx_reg[8]) // new RX data
+ rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; // valid rx data (= clear rx_tready inverted bit[8])
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ tx_reg <= 0;
+ else if ((ctrl_reg[0] == 1'b1)) // TX flush
+ tx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) // Write and set valid pending
+ tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (tx_tready & tx_tvalid) //& tx_reg[8]) // clear TX valid pending when req and ack
+ tx_reg[8] <= 1'b0; // clear valid when TX data acknowledged
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ ctrl_reg <= 8'b00000100;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3))
+ ctrl_reg[7:0] <= S_AXI_WDATA[7:0];
+ end
+
+ // Implement write response logic generation
+ // The write response and response valid signals are asserted by the slave
+ // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ // This marks the acceptance of address and indicates the status of
+ // write transaction.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_bvalid <= 0;
+ axi_bresp <= 2'b0;
+ end
+ else
+ begin
+ if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+ begin
+ // indicates a valid write response is available
+ axi_bvalid <= 1'b1;
+ axi_bresp <= 2'b0; // 'OKAY' response
+ end // work error responses in future
+ else
+ begin
+ if (S_AXI_BREADY && axi_bvalid)
+ //check if bready is asserted while bvalid is high)
+ //(there is a possibility that bready is always asserted high)
+ begin
+ axi_bvalid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // Implement axi_arready generation
+ // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ // S_AXI_ARVALID is asserted. axi_awready is
+ // de-asserted when reset (active low) is asserted.
+ // The read address is also latched when S_AXI_ARVALID is
+ // asserted. axi_araddr is reset to zero on reset assertion.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_arready <= 1'b0;
+ axi_araddr <= 32'b0;
+ end
+ else
+ begin
+ if (~axi_arready && S_AXI_ARVALID)
+ begin
+ // indicates that the slave has acceped the valid read address
+ axi_arready <= 1'b1;
+ // Read address latching
+ axi_araddr <= S_AXI_ARADDR;
+ end
+ else
+ begin
+ axi_arready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_arvalid generation
+ // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ // data are available on the axi_rdata bus at this instance. The
+ // assertion of axi_rvalid marks the validity of read data on the
+ // bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ // is deasserted on reset (active low). axi_rresp and axi_rdata are
+ // cleared to zero on reset (active low).
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rvalid <= 0;
+ axi_rresp <= 0;
+ end
+ else
+ begin
+ if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+ begin
+ // Valid read data is available at the read data bus
+ axi_rvalid <= 1'b1;
+ axi_rresp <= 2'b0; // 'OKAY' response
+ end
+ else if (axi_rvalid && S_AXI_RREADY)
+ begin
+ // Read data is accepted by the master
+ axi_rvalid <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and read logic generation
+ // Slave register read enable is asserted when valid address is available
+ // and the slave is ready to accept the read address.
+ assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+ always @(*)
+ begin
+ // Address decoding for reading registers
+ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0 : reg_data_out <= rx_reg[7:0];
+ 2'h1 : reg_data_out <= tx_reg[7:0];
+ 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_empty, tx_empty, rx_full, rx_full};
+ 2'h3 : reg_data_out <= ctrl_reg;
+ default : reg_data_out <= 0;
+ endcase
+ end
+
+ // Output register or memory read data
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rdata <= 0;
+ end
+ else
+ begin
+ // When there is a valid read address (S_AXI_ARVALID) with
+ // acceptance of read address by the slave (axi_arready),
+ // output the read dada
+ if (slv_reg_rden)
+ begin
+ axi_rdata <= {24'h000000, reg_data_out}; // register read data
+ end
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl b/socket/xilinx_lib/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..fcf8a063ad02ac8d5e1c0cefd2eaf6c6e8339a41
--- /dev/null
+++ b/socket/xilinx_lib/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
@@ -0,0 +1,58 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_axi_s_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_axi_s_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to update C_axi_s_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to validate C_axi_s_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to update C_axi_s_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to validate C_axi_s_HIGHADDR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/component.xml b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..796d46a13ba0928a9546ea901b61a01f961810b6
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/component.xml
@@ -0,0 +1,643 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>ft1248x1_to_axi_streamio</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+</spirit:component>
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
new file mode 100644
index 0000000000000000000000000000000000000000..e82fe55bd07f5b2021117a733d5ad768f20a16cc
Binary files /dev/null and b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix differ
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
new file mode 100644
index 0000000000000000000000000000000000000000..c669ec19a796217b231dd0575337608f84445beb
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
@@ -0,0 +1,42 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire syn_del_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign syn_del_o = (testmode_i) ? asyn_i : sync_stage3;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..a089edf83efd967f56efb3ce3e55ed1d93a63d19
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2022-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+ module ft1248x1_to_axi_streamio_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Stream Bus Interface rxd8
+ parameter integer C_rxd8_TDATA_WIDTH = 8,
+
+ // Parameters of Axi Stream Bus Interface txd8
+ parameter integer C_txd8_TDATA_WIDTH = 8
+ )
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+
+ input wire aclk, // external primary clock
+ input wire aresetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+wire ft_miosio_i_del;
+
+SYNCHRONIZER_EDGES u_sync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .syn_del_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .syn_del_o(),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_din (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_miosio_i),
+ .syn_o( ),
+ .syn_del_o(ft_miosio_i_del),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i_del, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, ft_miosio_i_del, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+
+/*
+reg [8:0] rxstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+*/
+
+// shift TXD on rising edge of clock
+reg [8:0] txd_sr;
+// rewrite for clocked
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & rxd_tvalid_i & (ft_state == 5'b00111))
+ txd_sr <= rxd_tdata8_i;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+assign rxd_tready_o = (ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01110)); // hold until final shift
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+//assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+assign ft_miso_o = (ft_ssn_i) ? !rxd_tvalid_i : ((ft_state == 5'b00111) & ((ft_cmd_txd) ? txstream[8]: !rxd_tvalid_i));
+
+endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..03004bea96fe4c5e9ea0984b905d5f7a4b91d771
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_axi_streamio_v1_0_rxd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..28cc34eafd0d52416bcfd2c8472fcda1245cd9a6
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_axi_streamio_v1_0_txd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..7cc581a635a8bd18d2224fc4f7b002adf2093b95
Binary files /dev/null and b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip differ
diff --git a/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f4b8c38737c46cbcd6d7a1adc43b9844e6b2e07f
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
@@ -0,0 +1,35 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+
+}
+
+proc update_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to update C_rxd8_TDATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to validate C_rxd8_TDATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to update C_txd8_TDATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to validate C_txd8_TDATA_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH { MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_rxd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_txd8_TDATA_WIDTH { MODELPARAM_VALUE.C_txd8_TDATA_WIDTH PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_txd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_txd8_TDATA_WIDTH}
+}
+
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/bd/bd.tcl b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/component.xml b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c9d8d6e573fef4d3a7f1d643e634a02f82032d93
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/component.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:vendor>soclabs.org</spirit:vendor>
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+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
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+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
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+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>/AXI_Infrastructure</xilinx:taxonomy>
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+ <xilinx:taxonomy>/Embedded_Processing/Debug_&_Verification/Debug</xilinx:taxonomy>
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diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix
new file mode 100644
index 0000000000000000000000000000000000000000..1b2410ad1ecde98574e898028f41ad55c1c8f3b1
Binary files /dev/null and b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix differ
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..822ab4cd47a344ec599d082d80384686bdb6360d
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
@@ -0,0 +1,75 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Slave Bus Interface RXD8
+ parameter integer C_RXD8_TDATA_WIDTH = 32,
+
+ // Parameters of Axi Master Bus Interface TXD8
+ parameter integer C_TXD8_TDATA_WIDTH = 32,
+ parameter integer C_TXD8_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Slave Bus Interface RXD8
+ input wire rxd8_aclk,
+ input wire rxd8_aresetn,
+ output wire rxd8_tready,
+ input wire [C_RXD8_TDATA_WIDTH-1 : 0] rxd8_tdata,
+ input wire [(C_RXD8_TDATA_WIDTH/8)-1 : 0] rxd8_tstrb,
+ input wire rxd8_tlast,
+ input wire rxd8_tvalid,
+
+ // Ports of Axi Master Bus Interface TXD8
+ input wire txd8_aclk,
+ input wire txd8_aresetn,
+ output wire txd8_tvalid,
+ output wire [C_TXD8_TDATA_WIDTH-1 : 0] txd8_tdata,
+ output wire [(C_TXD8_TDATA_WIDTH/8)-1 : 0] txd8_tstrb,
+ output wire txd8_tlast,
+ input wire txd8_tready
+ );
+// Instantiation of Axi Bus Interface RXD8
+ ft1248x1_to_stream8_v1_0_RXD8 # (
+ .C_S_AXIS_TDATA_WIDTH(C_RXD8_TDATA_WIDTH)
+ ) ft1248x1_to_stream8_v1_0_RXD8_inst (
+ .S_AXIS_ACLK(rxd8_aclk),
+ .S_AXIS_ARESETN(rxd8_aresetn),
+ .S_AXIS_TREADY(rxd8_tready),
+ .S_AXIS_TDATA(rxd8_tdata),
+ .S_AXIS_TSTRB(rxd8_tstrb),
+ .S_AXIS_TLAST(rxd8_tlast),
+ .S_AXIS_TVALID(rxd8_tvalid)
+ );
+
+// Instantiation of Axi Bus Interface TXD8
+ ft1248x1_to_stream8_v1_0_TXD8 # (
+ .C_M_AXIS_TDATA_WIDTH(C_TXD8_TDATA_WIDTH),
+ .C_M_START_COUNT(C_TXD8_START_COUNT)
+ ) ft1248x1_to_stream8_v1_0_TXD8_inst (
+ .M_AXIS_ACLK(txd8_aclk),
+ .M_AXIS_ARESETN(txd8_aresetn),
+ .M_AXIS_TVALID(txd8_tvalid),
+ .M_AXIS_TDATA(txd8_tdata),
+ .M_AXIS_TSTRB(txd8_tstrb),
+ .M_AXIS_TLAST(txd8_tlast),
+ .M_AXIS_TREADY(txd8_tready)
+ );
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..9b39ac62c1aa1246d5b566160b5bd7b5dd1d07ad
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_RXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..3abf9f8a3c52a9a6716e09c985c2a15faa383be5
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_TXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/ip_project_archive.zip b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/ip_project_archive.zip
new file mode 100755
index 0000000000000000000000000000000000000000..e67e74bbc9ca5ffffb895c6ce630825d07197fa2
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diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..bd8f20f74f0cc9c44da89578d526ab1afbd7f276
Binary files /dev/null and b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip differ
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
new file mode 100755
index 0000000000000000000000000000000000000000..6c55abc8d956769a1ca142d910603d780445a4ca
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
@@ -0,0 +1,187 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+
+module ft1248x1_to_stream8
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO
+//
+// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
+
+ input wire clk, // external primary clock
+ input wire resetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+//wire ft_ssn_rising;
+//wire ft_ssn_falling;
+
+SYNCHRONIZER_EDGES u_xync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_xync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] rxstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+
+// shift TXD on rising edge of clock
+reg [7:0] txd_sr;
+// rewrite for clocked
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111))
+ txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+
+
+endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/synclib.v b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/synclib.v
new file mode 100755
index 0000000000000000000000000000000000000000..1daf61f27dffed42591278f8e46a4239a46554a2
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/src/synclib.v
@@ -0,0 +1,139 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
+
+module SYNCHRONIZER_RST_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_RST_HI (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= 1'b1;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+
+module NRST_SYNCHRONIZER_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,output wire synreset_n_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign synreset_n_o = (testmode_i) ? reset_n_i : sync_stage2;
+
+endmodule
diff --git a/socket/xilinx_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0db18e9a9d18f3e4b14481f7664b048781110ca3
--- /dev/null
+++ b/socket/xilinx_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/bd/bd.tcl b/socket/xilinx_lib/uart_to_AXI_master_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/component.xml b/socket/xilinx_lib/uart_to_AXI_master_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..173a620b0216a055aa49e21a9a1853f6062e3d2b
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/component.xml
@@ -0,0 +1,1707 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>user.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>uart_to_AXI_master</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="M00_AXI"/>
+ </spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWLEN</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awlen</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awsize</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awburst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awlock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWCACHE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awcache</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWQOS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awqos</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wlast</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wuser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_buser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARLEN</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arlen</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arsize</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arburst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arlock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARCACHE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arcache</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARQOS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arqos</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_aruser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rlast</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_ruser</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI_RST</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI_CLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_CLK.ASSOCIATED_BUSIF">M00_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_CLK.ASSOCIATED_RESET">m00_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:addressSpaces>
+ <spirit:addressSpace>
+ <spirit:name>M00_AXI</spirit:name>
+ <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="0" spirit:maximum="4294967296" spirit:rangeType="long">4294967296</spirit:range>
+ <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH')) - 1) + 1">32</spirit:width>
+ </spirit:addressSpace>
+ </spirit:addressSpaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>uart_to_AXI_master_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>38b2cf1f</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>uart_to_AXI_master_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>38b2cf1f</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>35a319c8</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>45a2f450</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>UART_RX</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>UART_TX</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>m00_axi_aclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
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+ </spirit:wireTypeDef>
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+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_TARGET_SLAVE_BASE_ADDR</spirit:name>
+ <spirit:displayName>C M00 AXI TARGET SLAVE BASE ADDR</spirit:displayName>
+ <spirit:description>Base address of targeted slave</spirit:description>
+ <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR" spirit:order="3" spirit:bitStringLength="32">0x40000000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_BURST_LEN</spirit:name>
+ <spirit:displayName>C M00 AXI BURST LEN</spirit:displayName>
+ <spirit:description>Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_BURST_LEN" spirit:choiceRef="choice_list_85010fde" spirit:order="4">16</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_ID_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ID WIDTH</spirit:displayName>
+ <spirit:description>Thread ID Width</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_ID_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_ID_WIDTH'))))" spirit:order="5" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH" spirit:order="6" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH" spirit:order="7" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_AWUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI AWUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Write Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH'))))" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_ARUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ARUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Read Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH'))))" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_WUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI WUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Write Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_WUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_WUSER_WIDTH'))))" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_RUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI RUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Read Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_RUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_RUSER_WIDTH'))))" spirit:order="11" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_M00_AXI_BUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI BUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Response Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_M00_AXI_BUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_M00_AXI_BUSER_WIDTH'))))" spirit:order="12" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>CLK_SPEED</spirit:name>
+ <spirit:displayName>Clk Speed</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLK_SPEED">10000000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>UART_BAUD_RATE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.UART_BAUD_RATE">115200</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
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+ <spirit:name>choice_list_6fc15197</spirit:name>
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+ <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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+ <spirit:file>
+ <spirit:name>src/dbg_bridge.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
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+ <spirit:name>src/dbg_bridge_fifo.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
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+ <spirit:name>src/dbg_bridge_uart.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
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+ <spirit:file>
+ <spirit:name>hdl/uart_to_AXI_master_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_c45cfbca</spirit:userFileType>
+ </spirit:file>
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+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/uart_to_AXI_master_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
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+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
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+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_35a319c8</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>Uart to AXI master packaged from https://github.com/ultraembedded/core_dbg_bridge</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_TARGET_SLAVE_BASE_ADDR</spirit:name>
+ <spirit:displayName>C M00 AXI TARGET SLAVE BASE ADDR</spirit:displayName>
+ <spirit:description>Base address of targeted slave</spirit:description>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR" spirit:order="3" spirit:bitStringLength="32">0x40000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_BURST_LEN</spirit:name>
+ <spirit:displayName>C M00 AXI BURST LEN</spirit:displayName>
+ <spirit:description>Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_BURST_LEN" spirit:choiceRef="choice_list_85010fde" spirit:order="4">16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_ID_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ID WIDTH</spirit:displayName>
+ <spirit:description>Thread ID Width</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_ID_WIDTH" spirit:order="5" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_ADDR_WIDTH" spirit:order="6" spirit:rangeType="long">32</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_M00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="7">32</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_M00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_AWUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI AWUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Write Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_ARUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI ARUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Read Address Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_WUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI WUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Write Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_WUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_M00_AXI_RUSER_WIDTH</spirit:name>
+ <spirit:displayName>C M00 AXI RUSER WIDTH</spirit:displayName>
+ <spirit:description>Width of User Read Data Bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_RUSER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
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+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="372f74e8"/>
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+</spirit:component>
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v b/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..8baf1d3ac7e01acfa93a521ded72c233c3ff5404
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
@@ -0,0 +1,125 @@
+
+`timescale 1 ns / 1 ps
+
+ module uart_to_AXI_master_v1_0 #
+ (
+ // Users to add parameters here
+ parameter integer CLK_SPEED = 10000000,
+ parameter integer UART_BAUD_RATE = 115200,
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Master Bus Interface M00_AXI
+ parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
+ parameter integer C_M00_AXI_BURST_LEN = 16,
+ parameter integer C_M00_AXI_ID_WIDTH = 4,
+ parameter integer C_M00_AXI_ADDR_WIDTH = 32,
+ parameter integer C_M00_AXI_DATA_WIDTH = 32,
+ parameter integer C_M00_AXI_AWUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_ARUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_WUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_RUSER_WIDTH = 4,
+ parameter integer C_M00_AXI_BUSER_WIDTH = 4
+ )
+ (
+ // Users to add ports her
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Master Bus Interface M00_AXI
+ input wire UART_RX,
+ output wire UART_TX,
+ input wire m00_axi_aclk,
+ input wire m00_axi_aresetn,
+ output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
+ output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
+ output wire [7 : 0] m00_axi_awlen,
+ output wire [2 : 0] m00_axi_awsize,
+ output wire [1 : 0] m00_axi_awburst,
+ output wire m00_axi_awlock,
+ output wire [3 : 0] m00_axi_awcache,
+ output wire [2 : 0] m00_axi_awprot,
+ output wire [3 : 0] m00_axi_awqos,
+ output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
+ output wire m00_axi_awvalid,
+ input wire m00_axi_awready,
+ output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
+ output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
+ output wire m00_axi_wlast,
+ output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
+ output wire m00_axi_wvalid,
+ input wire m00_axi_wready,
+ input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
+ input wire [1 : 0] m00_axi_bresp,
+ input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
+ input wire m00_axi_bvalid,
+ output wire m00_axi_bready,
+ output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
+ output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
+ output wire [7 : 0] m00_axi_arlen,
+ output wire [2 : 0] m00_axi_arsize,
+ output wire [1 : 0] m00_axi_arburst,
+ output wire m00_axi_arlock,
+ output wire [3 : 0] m00_axi_arcache,
+ output wire [2 : 0] m00_axi_arprot,
+ output wire [3 : 0] m00_axi_arqos,
+ output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
+ output wire m00_axi_arvalid,
+ input wire m00_axi_arready,
+ input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
+ input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
+ input wire [1 : 0] m00_axi_rresp,
+ input wire m00_axi_rlast,
+ input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
+ input wire m00_axi_rvalid,
+ output wire m00_axi_rready
+ );
+// Instantiation of Axi Bus Interface M00_AXI
+
+ // Add user logic here
+ dbg_bridge #(.CLK_FREQ(CLK_SPEED),
+ .UART_SPEED(UART_BAUD_RATE),
+ .AXI_ID(4'd0),
+ .GPIO_ADDRESS(32'hf0000000),
+ .STS_ADDRESS(32'hf0000004))
+ dbg_bridge_inst (
+ .clk_i (m00_axi_aclk),
+ .rst_i (~m00_axi_aresetn),
+ .uart_rxd_i (UART_RX),
+ .uart_txd_o (UART_TX),
+ .gpio_inputs_i (),
+ .gpio_outputs_o (),
+ .mem_awready_i (m00_axi_awready),
+ .mem_wready_i (m00_axi_wready),
+ .mem_bvalid_i (m00_axi_bvalid),
+ .mem_bresp_i (m00_axi_bresp),
+ .mem_bid_i (m00_axi_bid),
+ .mem_arready_i (m00_axi_arready),
+ .mem_rvalid_i (m00_axi_rvalid),
+ .mem_rdata_i (m00_axi_rdata),
+ .mem_rresp_i (m00_axi_rresp),
+ .mem_rid_i (m00_axi_rid),
+ .mem_rlast_i (m00_axi_rlast),
+ .mem_awvalid_o (m00_axi_awvalid),
+ .mem_awaddr_o (m00_axi_awaddr),
+ .mem_awid_o (m00_axi_awid),
+ .mem_awlen_o (m00_axi_awlen),
+ .mem_awburst_o (m00_axi_awburst),
+ .mem_wvalid_o (m00_axi_wvalid),
+ .mem_wdata_o (m00_axi_wdata),
+ .mem_wstrb_o (m00_axi_wstrb),
+ .mem_wlast_o (m00_axi_wlast),
+ .mem_bready_o (m00_axi_bready),
+ .mem_arvalid_o (m00_axi_arvalid),
+ .mem_araddr_o (m00_axi_araddr),
+ .mem_arid_o (m00_axi_arid),
+ .mem_arlen_o (m00_axi_arlen),
+ .mem_arburst_o (m00_axi_arburst),
+ .mem_rready_o (m00_axi_rready)
+ );
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v b/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
new file mode 100644
index 0000000000000000000000000000000000000000..ac7d45594a28cc78c48e2852cb8f6e1070be8813
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
@@ -0,0 +1,907 @@
+
+`timescale 1 ns / 1 ps
+
+ module uart_to_AXI_master_v1_0_M00_AXI #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Base address of targeted slave
+ parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
+ // Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
+ parameter integer C_M_AXI_BURST_LEN = 16,
+ // Thread ID Width
+ parameter integer C_M_AXI_ID_WIDTH = 1,
+ // Width of Address Bus
+ parameter integer C_M_AXI_ADDR_WIDTH = 32,
+ // Width of Data Bus
+ parameter integer C_M_AXI_DATA_WIDTH = 32,
+ // Width of User Write Address Bus
+ parameter integer C_M_AXI_AWUSER_WIDTH = 0,
+ // Width of User Read Address Bus
+ parameter integer C_M_AXI_ARUSER_WIDTH = 0,
+ // Width of User Write Data Bus
+ parameter integer C_M_AXI_WUSER_WIDTH = 0,
+ // Width of User Read Data Bus
+ parameter integer C_M_AXI_RUSER_WIDTH = 0,
+ // Width of User Response Bus
+ parameter integer C_M_AXI_BUSER_WIDTH = 0
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Initiate AXI transactions
+ input wire INIT_AXI_TXN,
+ // Asserts when transaction is complete
+ output wire TXN_DONE,
+ // Asserts when ERROR is detected
+ output reg ERROR,
+ // Global Clock Signal.
+ input wire M_AXI_ACLK,
+ // Global Reset Singal. This Signal is Active Low
+ input wire M_AXI_ARESETN,
+ // Master Interface Write Address ID
+ output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
+ // Master Interface Write Address
+ output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
+ // Burst length. The burst length gives the exact number of transfers in a burst
+ output wire [7 : 0] M_AXI_AWLEN,
+ // Burst size. This signal indicates the size of each transfer in the burst
+ output wire [2 : 0] M_AXI_AWSIZE,
+ // Burst type. The burst type and the size information,
+ // determine how the address for each transfer within the burst is calculated.
+ output wire [1 : 0] M_AXI_AWBURST,
+ // Lock type. Provides additional information about the
+ // atomic characteristics of the transfer.
+ output wire M_AXI_AWLOCK,
+ // Memory type. This signal indicates how transactions
+ // are required to progress through a system.
+ output wire [3 : 0] M_AXI_AWCACHE,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ output wire [2 : 0] M_AXI_AWPROT,
+ // Quality of Service, QoS identifier sent for each write transaction.
+ output wire [3 : 0] M_AXI_AWQOS,
+ // Optional User-defined signal in the write address channel.
+ output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
+ // Write address valid. This signal indicates that
+ // the channel is signaling valid write address and control information.
+ output wire M_AXI_AWVALID,
+ // Write address ready. This signal indicates that
+ // the slave is ready to accept an address and associated control signals
+ input wire M_AXI_AWREADY,
+ // Master Interface Write Data.
+ output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
+ // Write strobes. This signal indicates which byte
+ // lanes hold valid data. There is one write strobe
+ // bit for each eight bits of the write data bus.
+ output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
+ // Write last. This signal indicates the last transfer in a write burst.
+ output wire M_AXI_WLAST,
+ // Optional User-defined signal in the write data channel.
+ output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available
+ output wire M_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ input wire M_AXI_WREADY,
+ // Master Interface Write Response.
+ input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
+ // Write response. This signal indicates the status of the write transaction.
+ input wire [1 : 0] M_AXI_BRESP,
+ // Optional User-defined signal in the write response channel
+ input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
+ // Write response valid. This signal indicates that the
+ // channel is signaling a valid write response.
+ input wire M_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ output wire M_AXI_BREADY,
+ // Master Interface Read Address.
+ output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
+ // Read address. This signal indicates the initial
+ // address of a read burst transaction.
+ output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
+ // Burst length. The burst length gives the exact number of transfers in a burst
+ output wire [7 : 0] M_AXI_ARLEN,
+ // Burst size. This signal indicates the size of each transfer in the burst
+ output wire [2 : 0] M_AXI_ARSIZE,
+ // Burst type. The burst type and the size information,
+ // determine how the address for each transfer within the burst is calculated.
+ output wire [1 : 0] M_AXI_ARBURST,
+ // Lock type. Provides additional information about the
+ // atomic characteristics of the transfer.
+ output wire M_AXI_ARLOCK,
+ // Memory type. This signal indicates how transactions
+ // are required to progress through a system.
+ output wire [3 : 0] M_AXI_ARCACHE,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ output wire [2 : 0] M_AXI_ARPROT,
+ // Quality of Service, QoS identifier sent for each read transaction
+ output wire [3 : 0] M_AXI_ARQOS,
+ // Optional User-defined signal in the read address channel.
+ output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
+ // Write address valid. This signal indicates that
+ // the channel is signaling valid read address and control information
+ output wire M_AXI_ARVALID,
+ // Read address ready. This signal indicates that
+ // the slave is ready to accept an address and associated control signals
+ input wire M_AXI_ARREADY,
+ // Read ID tag. This signal is the identification tag
+ // for the read data group of signals generated by the slave.
+ input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
+ // Master Read Data
+ input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
+ // Read response. This signal indicates the status of the read transfer
+ input wire [1 : 0] M_AXI_RRESP,
+ // Read last. This signal indicates the last transfer in a read burst
+ input wire M_AXI_RLAST,
+ // Optional User-defined signal in the read address channel.
+ input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
+ // Read valid. This signal indicates that the channel
+ // is signaling the required read data.
+ input wire M_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ output wire M_AXI_RREADY
+ );
+
+
+ // function called clogb2 that returns an integer which has the
+ //value of the ceiling of the log base 2
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // C_TRANSACTIONS_NUM is the width of the index counter for
+ // number of write or read transaction.
+ localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1);
+
+ // Burst length for transactions, in C_M_AXI_DATA_WIDTHs.
+ // Non-2^n lengths will eventually cause bursts across 4K address boundaries.
+ localparam integer C_MASTER_LENGTH = 12;
+ // total number of burst transfers is master length divided by burst length and burst size
+ localparam integer C_NO_BURSTS_REQ = C_MASTER_LENGTH-clogb2((C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8)-1);
+ // Example State machine to initialize counter, initialize write transactions,
+ // initialize read transactions and comparison of read data with the
+ // written data words.
+ parameter [1:0] IDLE = 2'b00, // This state initiates AXI4Lite transaction
+ // after the state machine changes state to INIT_WRITE
+ // when there is 0 to 1 transition on INIT_AXI_TXN
+ INIT_WRITE = 2'b01, // This state initializes write transaction,
+ // once writes are done, the state machine
+ // changes state to INIT_READ
+ INIT_READ = 2'b10, // This state initializes read transaction
+ // once reads are done, the state machine
+ // changes state to INIT_COMPARE
+ INIT_COMPARE = 2'b11; // This state issues the status of comparison
+ // of the written data with the read data
+
+ reg [1:0] mst_exec_state;
+
+ // AXI4LITE signals
+ //AXI4 internal temp signals
+ reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awvalid;
+ reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
+ reg axi_wlast;
+ reg axi_wvalid;
+ reg axi_bready;
+ reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arvalid;
+ reg axi_rready;
+ //write beat count in a burst
+ reg [C_TRANSACTIONS_NUM : 0] write_index;
+ //read beat count in a burst
+ reg [C_TRANSACTIONS_NUM : 0] read_index;
+ //size of C_M_AXI_BURST_LEN length burst in bytes
+ wire [C_TRANSACTIONS_NUM+2 : 0] burst_size_bytes;
+ //The burst counters are used to track the number of burst transfers of C_M_AXI_BURST_LEN burst length needed to transfer 2^C_MASTER_LENGTH bytes of data.
+ reg [C_NO_BURSTS_REQ : 0] write_burst_counter;
+ reg [C_NO_BURSTS_REQ : 0] read_burst_counter;
+ reg start_single_burst_write;
+ reg start_single_burst_read;
+ reg writes_done;
+ reg reads_done;
+ reg error_reg;
+ reg compare_done;
+ reg read_mismatch;
+ reg burst_write_active;
+ reg burst_read_active;
+ reg [C_M_AXI_DATA_WIDTH-1 : 0] expected_rdata;
+ //Interface response error flags
+ wire write_resp_error;
+ wire read_resp_error;
+ wire wnext;
+ wire rnext;
+ reg init_txn_ff;
+ reg init_txn_ff2;
+ reg init_txn_edge;
+ wire init_txn_pulse;
+
+
+ // I/O Connections assignments
+
+ //I/O Connections. Write Address (AW)
+ assign M_AXI_AWID = 'b0;
+ //The AXI address is a concatenation of the target base address + active offset range
+ assign M_AXI_AWADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
+ //Burst LENgth is number of transaction beats, minus 1
+ assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1;
+ //Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
+ assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
+ //INCR burst type is usually used, except for keyhole bursts
+ assign M_AXI_AWBURST = 2'b01;
+ assign M_AXI_AWLOCK = 1'b0;
+ //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
+ assign M_AXI_AWCACHE = 4'b0010;
+ assign M_AXI_AWPROT = 3'h0;
+ assign M_AXI_AWQOS = 4'h0;
+ assign M_AXI_AWUSER = 'b1;
+ assign M_AXI_AWVALID = axi_awvalid;
+ //Write Data(W)
+ assign M_AXI_WDATA = axi_wdata;
+ //All bursts are complete and aligned in this example
+ assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
+ assign M_AXI_WLAST = axi_wlast;
+ assign M_AXI_WUSER = 'b0;
+ assign M_AXI_WVALID = axi_wvalid;
+ //Write Response (B)
+ assign M_AXI_BREADY = axi_bready;
+ //Read Address (AR)
+ assign M_AXI_ARID = 'b0;
+ assign M_AXI_ARADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_araddr;
+ //Burst LENgth is number of transaction beats, minus 1
+ assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1;
+ //Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
+ assign M_AXI_ARSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
+ //INCR burst type is usually used, except for keyhole bursts
+ assign M_AXI_ARBURST = 2'b01;
+ assign M_AXI_ARLOCK = 1'b0;
+ //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
+ assign M_AXI_ARCACHE = 4'b0010;
+ assign M_AXI_ARPROT = 3'h0;
+ assign M_AXI_ARQOS = 4'h0;
+ assign M_AXI_ARUSER = 'b1;
+ assign M_AXI_ARVALID = axi_arvalid;
+ //Read and Read Response (R)
+ assign M_AXI_RREADY = axi_rready;
+ //Example design I/O
+ assign TXN_DONE = compare_done;
+ //Burst size in bytes
+ assign burst_size_bytes = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
+ assign init_txn_pulse = (!init_txn_ff2) && init_txn_ff;
+
+
+ //Generate a pulse to initiate AXI transaction.
+ always @(posedge M_AXI_ACLK)
+ begin
+ // Initiates AXI transaction delay
+ if (M_AXI_ARESETN == 0 )
+ begin
+ init_txn_ff <= 1'b0;
+ init_txn_ff2 <= 1'b0;
+ end
+ else
+ begin
+ init_txn_ff <= INIT_AXI_TXN;
+ init_txn_ff2 <= init_txn_ff;
+ end
+ end
+
+
+ //--------------------
+ //Write Address Channel
+ //--------------------
+
+ // The purpose of the write address channel is to request the address and
+ // command information for the entire transaction. It is a single beat
+ // of information.
+
+ // The AXI4 Write address channel in this example will continue to initiate
+ // write commands as fast as it is allowed by the slave/interconnect.
+ // The address will be incremented on each accepted address transaction,
+ // by burst_size_byte to point to the next address.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_awvalid <= 1'b0;
+ end
+ // If previously not valid , start next transaction
+ else if (~axi_awvalid && start_single_burst_write)
+ begin
+ axi_awvalid <= 1'b1;
+ end
+ /* Once asserted, VALIDs cannot be deasserted, so axi_awvalid
+ must wait until transaction is accepted */
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ axi_awvalid <= 1'b0;
+ end
+ else
+ axi_awvalid <= axi_awvalid;
+ end
+
+
+ // Next address after AWREADY indicates previous address acceptance
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ axi_awaddr <= 'b0;
+ end
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ axi_awaddr <= axi_awaddr + burst_size_bytes;
+ end
+ else
+ axi_awaddr <= axi_awaddr;
+ end
+
+
+ //--------------------
+ //Write Data Channel
+ //--------------------
+
+ //The write data will continually try to push write data across the interface.
+
+ //The amount of data accepted will depend on the AXI slave and the AXI
+ //Interconnect settings, such as if there are FIFOs enabled in interconnect.
+
+ //Note that there is no explicit timing relationship to the write address channel.
+ //The write channel has its own throttling flag, separate from the AW channel.
+
+ //Synchronization between the channels must be determined by the user.
+
+ //The simpliest but lowest performance would be to only issue one address write
+ //and write data burst at a time.
+
+ //In this example they are kept in sync by using the same address increment
+ //and burst sizes. Then the AW and W channels have their transactions measured
+ //with threshold counters as part of the user logic, to make sure neither
+ //channel gets too far ahead of each other.
+
+ //Forward movement occurs when the write channel is valid and ready
+
+ assign wnext = M_AXI_WREADY & axi_wvalid;
+
+ // WVALID logic, similar to the axi_awvalid always block above
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_wvalid <= 1'b0;
+ end
+ // If previously not valid, start next transaction
+ else if (~axi_wvalid && start_single_burst_write)
+ begin
+ axi_wvalid <= 1'b1;
+ end
+ /* If WREADY and too many writes, throttle WVALID
+ Once asserted, VALIDs cannot be deasserted, so WVALID
+ must wait until burst is complete with WLAST */
+ else if (wnext && axi_wlast)
+ axi_wvalid <= 1'b0;
+ else
+ axi_wvalid <= axi_wvalid;
+ end
+
+
+ //WLAST generation on the MSB of a counter underflow
+ // WVALID logic, similar to the axi_awvalid always block above
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_wlast <= 1'b0;
+ end
+ // axi_wlast is asserted when the write index
+ // count reaches the penultimate count to synchronize
+ // with the last write data when write_index is b1111
+ // else if (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
+ else if (((write_index == C_M_AXI_BURST_LEN-2 && C_M_AXI_BURST_LEN >= 2) && wnext) || (C_M_AXI_BURST_LEN == 1 ))
+ begin
+ axi_wlast <= 1'b1;
+ end
+ // Deassrt axi_wlast when the last write data has been
+ // accepted by the slave with a valid response
+ else if (wnext)
+ axi_wlast <= 1'b0;
+ else if (axi_wlast && C_M_AXI_BURST_LEN == 1)
+ axi_wlast <= 1'b0;
+ else
+ axi_wlast <= axi_wlast;
+ end
+
+
+ /* Burst length counter. Uses extra counter register bit to indicate terminal
+ count to reduce decode logic */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_write == 1'b1)
+ begin
+ write_index <= 0;
+ end
+ else if (wnext && (write_index != C_M_AXI_BURST_LEN-1))
+ begin
+ write_index <= write_index + 1;
+ end
+ else
+ write_index <= write_index;
+ end
+
+
+ /* Write Data Generator
+ Data pattern is only a simple incrementing count from 0 for each burst */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ axi_wdata <= 'b1;
+ //else if (wnext && axi_wlast)
+ // axi_wdata <= 'b0;
+ else if (wnext)
+ axi_wdata <= axi_wdata + 1;
+ else
+ axi_wdata <= axi_wdata;
+ end
+
+
+ //----------------------------
+ //Write Response (B) Channel
+ //----------------------------
+
+ //The write response channel provides feedback that the write has committed
+ //to memory. BREADY will occur when all of the data and the write address
+ //has arrived and been accepted by the slave.
+
+ //The write issuance (number of outstanding write addresses) is started by
+ //the Address Write transfer, and is completed by a BREADY/BRESP.
+
+ //While negating BREADY will eventually throttle the AWREADY signal,
+ //it is best not to throttle the whole data channel this way.
+
+ //The BRESP bit [1] is used indicate any errors from the interconnect or
+ //slave for the entire write burst. This example will capture the error
+ //into the ERROR output.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_bready <= 1'b0;
+ end
+ // accept/acknowledge bresp with axi_bready by the master
+ // when M_AXI_BVALID is asserted by slave
+ else if (M_AXI_BVALID && ~axi_bready)
+ begin
+ axi_bready <= 1'b1;
+ end
+ // deassert after one clock cycle
+ else if (axi_bready)
+ begin
+ axi_bready <= 1'b0;
+ end
+ // retain the previous value
+ else
+ axi_bready <= axi_bready;
+ end
+
+
+ //Flag any write response errors
+ assign write_resp_error = axi_bready & M_AXI_BVALID & M_AXI_BRESP[1];
+
+
+ //----------------------------
+ //Read Address Channel
+ //----------------------------
+
+ //The Read Address Channel (AW) provides a similar function to the
+ //Write Address channel- to provide the tranfer qualifiers for the burst.
+
+ //In this example, the read address increments in the same
+ //manner as the write address channel.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_arvalid <= 1'b0;
+ end
+ // If previously not valid , start next transaction
+ else if (~axi_arvalid && start_single_burst_read)
+ begin
+ axi_arvalid <= 1'b1;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ axi_arvalid <= 1'b0;
+ end
+ else
+ axi_arvalid <= axi_arvalid;
+ end
+
+
+ // Next address after ARREADY indicates previous address acceptance
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ axi_araddr <= 'b0;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ axi_araddr <= axi_araddr + burst_size_bytes;
+ end
+ else
+ axi_araddr <= axi_araddr;
+ end
+
+
+ //--------------------------------
+ //Read Data (and Response) Channel
+ //--------------------------------
+
+ // Forward movement occurs when the channel is valid and ready
+ assign rnext = M_AXI_RVALID && axi_rready;
+
+
+ // Burst length counter. Uses extra counter register bit to indicate
+ // terminal count to reduce decode logic
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_read)
+ begin
+ read_index <= 0;
+ end
+ else if (rnext && (read_index != C_M_AXI_BURST_LEN-1))
+ begin
+ read_index <= read_index + 1;
+ end
+ else
+ read_index <= read_index;
+ end
+
+
+ /*
+ The Read Data channel returns the results of the read request
+
+ In this example the data checker is always able to accept
+ more data, so no need to throttle the RREADY signal
+ */
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ axi_rready <= 1'b0;
+ end
+ // accept/acknowledge rdata/rresp with axi_rready by the master
+ // when M_AXI_RVALID is asserted by slave
+ else if (M_AXI_RVALID)
+ begin
+ if (M_AXI_RLAST && axi_rready)
+ begin
+ axi_rready <= 1'b0;
+ end
+ else
+ begin
+ axi_rready <= 1'b1;
+ end
+ end
+ // retain the previous value
+ end
+
+ //Check received read data against data generator
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ read_mismatch <= 1'b0;
+ end
+ //Only check data when RVALID is active
+ else if (rnext && (M_AXI_RDATA != expected_rdata))
+ begin
+ read_mismatch <= 1'b1;
+ end
+ else
+ read_mismatch <= 1'b0;
+ end
+
+ //Flag any read response errors
+ assign read_resp_error = axi_rready & M_AXI_RVALID & M_AXI_RRESP[1];
+
+
+ //----------------------------------------
+ //Example design read check data generator
+ //-----------------------------------------
+
+ //Generate expected read data to check against actual read data
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)// || M_AXI_RLAST)
+ expected_rdata <= 'b1;
+ else if (M_AXI_RVALID && axi_rready)
+ expected_rdata <= expected_rdata + 1;
+ else
+ expected_rdata <= expected_rdata;
+ end
+
+
+ //----------------------------------
+ //Example design error register
+ //----------------------------------
+
+ //Register and hold any data mismatches, or read/write interface errors
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ error_reg <= 1'b0;
+ end
+ else if (read_mismatch || write_resp_error || read_resp_error)
+ begin
+ error_reg <= 1'b1;
+ end
+ else
+ error_reg <= error_reg;
+ end
+
+
+ //--------------------------------
+ //Example design throttling
+ //--------------------------------
+
+ // For maximum port throughput, this user example code will try to allow
+ // each channel to run as independently and as quickly as possible.
+
+ // However, there are times when the flow of data needs to be throtted by
+ // the user application. This example application requires that data is
+ // not read before it is written and that the write channels do not
+ // advance beyond an arbitrary threshold (say to prevent an
+ // overrun of the current read address by the write address).
+
+ // From AXI4 Specification, 13.13.1: "If a master requires ordering between
+ // read and write transactions, it must ensure that a response is received
+ // for the previous transaction before issuing the next transaction."
+
+ // This example accomplishes this user application throttling through:
+ // -Reads wait for writes to fully complete
+ // -Address writes wait when not read + issued transaction counts pass
+ // a parameterized threshold
+ // -Writes wait when a not read + active data burst count pass
+ // a parameterized threshold
+
+ // write_burst_counter counter keeps track with the number of burst transaction initiated
+ // against the number of burst transactions the master needs to initiate
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
+ begin
+ write_burst_counter <= 'b0;
+ end
+ else if (M_AXI_AWREADY && axi_awvalid)
+ begin
+ if (write_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
+ begin
+ write_burst_counter <= write_burst_counter + 1'b1;
+ //write_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
+ end
+ end
+ else
+ write_burst_counter <= write_burst_counter;
+ end
+
+ // read_burst_counter counter keeps track with the number of burst transaction initiated
+ // against the number of burst transactions the master needs to initiate
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ begin
+ read_burst_counter <= 'b0;
+ end
+ else if (M_AXI_ARREADY && axi_arvalid)
+ begin
+ if (read_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
+ begin
+ read_burst_counter <= read_burst_counter + 1'b1;
+ //read_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
+ end
+ end
+ else
+ read_burst_counter <= read_burst_counter;
+ end
+
+
+ //implement master command interface state machine
+
+ always @ ( posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 1'b0 )
+ begin
+ // reset condition
+ // All the signals are assigned default values under reset condition
+ mst_exec_state <= IDLE;
+ start_single_burst_write <= 1'b0;
+ start_single_burst_read <= 1'b0;
+ compare_done <= 1'b0;
+ ERROR <= 1'b0;
+ end
+ else
+ begin
+
+ // state transition
+ case (mst_exec_state)
+
+ IDLE:
+ // This state is responsible to wait for user defined C_M_START_COUNT
+ // number of clock cycles.
+ if ( init_txn_pulse == 1'b1)
+ begin
+ mst_exec_state <= INIT_WRITE;
+ ERROR <= 1'b0;
+ compare_done <= 1'b0;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+
+ INIT_WRITE:
+ // This state is responsible to issue start_single_write pulse to
+ // initiate a write transaction. Write transactions will be
+ // issued until burst_write_active signal is asserted.
+ // write controller
+ if (writes_done)
+ begin
+ mst_exec_state <= INIT_READ;//
+ end
+ else
+ begin
+ mst_exec_state <= INIT_WRITE;
+
+ if (~axi_awvalid && ~start_single_burst_write && ~burst_write_active)
+ begin
+ start_single_burst_write <= 1'b1;
+ end
+ else
+ begin
+ start_single_burst_write <= 1'b0; //Negate to generate a pulse
+ end
+ end
+
+ INIT_READ:
+ // This state is responsible to issue start_single_read pulse to
+ // initiate a read transaction. Read transactions will be
+ // issued until burst_read_active signal is asserted.
+ // read controller
+ if (reads_done)
+ begin
+ mst_exec_state <= INIT_COMPARE;
+ end
+ else
+ begin
+ mst_exec_state <= INIT_READ;
+
+ if (~axi_arvalid && ~burst_read_active && ~start_single_burst_read)
+ begin
+ start_single_burst_read <= 1'b1;
+ end
+ else
+ begin
+ start_single_burst_read <= 1'b0; //Negate to generate a pulse
+ end
+ end
+
+ INIT_COMPARE:
+ // This state is responsible to issue the state of comparison
+ // of written data with the read data. If no error flags are set,
+ // compare_done signal will be asseted to indicate success.
+ //if (~error_reg)
+ begin
+ ERROR <= error_reg;
+ mst_exec_state <= IDLE;
+ compare_done <= 1'b1;
+ end
+ default :
+ begin
+ mst_exec_state <= IDLE;
+ end
+ endcase
+ end
+ end //MASTER_EXECUTION_PROC
+
+
+ // burst_write_active signal is asserted when there is a burst write transaction
+ // is initiated by the assertion of start_single_burst_write. burst_write_active
+ // signal remains asserted until the burst write is accepted by the slave
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ burst_write_active <= 1'b0;
+
+ //The burst_write_active is asserted when a write burst transaction is initiated
+ else if (start_single_burst_write)
+ burst_write_active <= 1'b1;
+ else if (M_AXI_BVALID && axi_bready)
+ burst_write_active <= 0;
+ end
+
+ // Check for last write completion.
+
+ // This logic is to qualify the last write count with the final write
+ // response. This demonstrates how to confirm that a write has been
+ // committed.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ writes_done <= 1'b0;
+
+ //The writes_done should be associated with a bready response
+ //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
+ else if (M_AXI_BVALID && (write_burst_counter[C_NO_BURSTS_REQ]) && axi_bready)
+ writes_done <= 1'b1;
+ else
+ writes_done <= writes_done;
+ end
+
+ // burst_read_active signal is asserted when there is a burst write transaction
+ // is initiated by the assertion of start_single_burst_write. start_single_burst_read
+ // signal remains asserted until the burst read is accepted by the master
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ burst_read_active <= 1'b0;
+
+ //The burst_write_active is asserted when a write burst transaction is initiated
+ else if (start_single_burst_read)
+ burst_read_active <= 1'b1;
+ else if (M_AXI_RVALID && axi_rready && M_AXI_RLAST)
+ burst_read_active <= 0;
+ end
+
+
+ // Check for last read completion.
+
+ // This logic is to qualify the last read count with the final read
+ // response. This demonstrates how to confirm that a read has been
+ // committed.
+
+ always @(posedge M_AXI_ACLK)
+ begin
+ if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
+ reads_done <= 1'b0;
+
+ //The reads_done should be associated with a rready response
+ //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
+ else if (M_AXI_RVALID && axi_rready && (read_index == C_M_AXI_BURST_LEN-1) && (read_burst_counter[C_NO_BURSTS_REQ]))
+ reads_done <= 1'b1;
+ else
+ reads_done <= reads_done;
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge.v b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge.v
new file mode 100644
index 0000000000000000000000000000000000000000..c410c75ded4129cdb5eb8d3c5674aa0012438ad1
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge.v
@@ -0,0 +1,623 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module dbg_bridge
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter CLK_FREQ = 24000000
+ ,parameter UART_SPEED = 115200
+ ,parameter AXI_ID = 4'd0
+ ,parameter GPIO_ADDRESS = 32'hf0000000
+ ,parameter STS_ADDRESS = 32'hf0000004
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input uart_rxd_i
+ ,input mem_awready_i
+ ,input mem_wready_i
+ ,input mem_bvalid_i
+ ,input [ 1:0] mem_bresp_i
+ ,input [ 3:0] mem_bid_i
+ ,input mem_arready_i
+ ,input mem_rvalid_i
+ ,input [ 31:0] mem_rdata_i
+ ,input [ 1:0] mem_rresp_i
+ ,input [ 3:0] mem_rid_i
+ ,input mem_rlast_i
+ ,input [ 31:0] gpio_inputs_i
+
+ // Outputs
+ ,output uart_txd_o
+ ,output mem_awvalid_o
+ ,output [ 31:0] mem_awaddr_o
+ ,output [ 3:0] mem_awid_o
+ ,output [ 7:0] mem_awlen_o
+ ,output [ 1:0] mem_awburst_o
+ ,output mem_wvalid_o
+ ,output [ 31:0] mem_wdata_o
+ ,output [ 3:0] mem_wstrb_o
+ ,output mem_wlast_o
+ ,output mem_bready_o
+ ,output mem_arvalid_o
+ ,output [ 31:0] mem_araddr_o
+ ,output [ 3:0] mem_arid_o
+ ,output [ 7:0] mem_arlen_o
+ ,output [ 1:0] mem_arburst_o
+ ,output mem_rready_o
+ ,output [ 31:0] gpio_outputs_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines
+//-----------------------------------------------------------------
+localparam REQ_WRITE = 8'h10;
+localparam REQ_READ = 8'h11;
+
+`define STATE_W 4
+`define STATE_R 3:0
+localparam STATE_IDLE = 4'd0;
+localparam STATE_LEN = 4'd2;
+localparam STATE_ADDR0 = 4'd3;
+localparam STATE_ADDR1 = 4'd4;
+localparam STATE_ADDR2 = 4'd5;
+localparam STATE_ADDR3 = 4'd6;
+localparam STATE_WRITE = 4'd7;
+localparam STATE_READ = 4'd8;
+localparam STATE_DATA0 = 4'd9;
+localparam STATE_DATA1 = 4'd10;
+localparam STATE_DATA2 = 4'd11;
+localparam STATE_DATA3 = 4'd12;
+
+//-----------------------------------------------------------------
+// Wires / Regs
+//-----------------------------------------------------------------
+wire uart_wr_w;
+wire [7:0] uart_wr_data_w;
+wire uart_wr_busy_w;
+
+wire uart_rd_w;
+wire [7:0] uart_rd_data_w;
+wire uart_rd_valid_w;
+
+wire uart_rx_error_w;
+
+wire tx_valid_w;
+wire [7:0] tx_data_w;
+wire tx_accept_w;
+wire read_skip_w;
+
+wire rx_valid_w;
+wire [7:0] rx_data_w;
+wire rx_accept_w;
+
+reg [31:0] mem_addr_q;
+reg mem_busy_q;
+reg mem_wr_q;
+
+reg [7:0] len_q;
+
+// Byte Index
+reg [1:0] data_idx_q;
+
+// Word storage
+reg [31:0] data_q;
+
+wire magic_addr_w = (mem_addr_q == GPIO_ADDRESS || mem_addr_q == STS_ADDRESS);
+
+//-----------------------------------------------------------------
+// UART core
+//-----------------------------------------------------------------
+dbg_bridge_uart
+#( .UART_DIVISOR_W(32) )
+u_uart
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // Control
+ .bit_div_i((CLK_FREQ / UART_SPEED) - 1),
+ .stop_bits_i(1'b0), // 0 = 1, 1 = 2
+
+ // Transmit
+ .wr_i(uart_wr_w),
+ .data_i(uart_wr_data_w),
+ .tx_busy_o(uart_wr_busy_w),
+
+ // Receive
+ .rd_i(uart_rd_w),
+ .data_o(uart_rd_data_w),
+ .rx_ready_o(uart_rd_valid_w),
+
+ .rx_err_o(uart_rx_error_w),
+
+ // UART pins
+ .rxd_i(uart_rxd_i),
+ .txd_o(uart_txd_o)
+);
+
+//-----------------------------------------------------------------
+// Output FIFO
+//-----------------------------------------------------------------
+wire uart_tx_pop_w = ~uart_wr_busy_w;
+
+dbg_bridge_fifo
+#(
+ .WIDTH(8),
+ .DEPTH(8),
+ .ADDR_W(3)
+)
+u_fifo_tx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // In
+ .push_i(tx_valid_w),
+ .data_in_i(tx_data_w),
+ .accept_o(tx_accept_w),
+
+ // Out
+ .pop_i(uart_tx_pop_w),
+ .data_out_o(uart_wr_data_w),
+ .valid_o(uart_wr_w)
+);
+
+//-----------------------------------------------------------------
+// Input FIFO
+//-----------------------------------------------------------------
+dbg_bridge_fifo
+#(
+ .WIDTH(8),
+ .DEPTH(8),
+ .ADDR_W(3)
+)
+u_fifo_rx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ // In
+ .push_i(uart_rd_valid_w),
+ .data_in_i(uart_rd_data_w),
+ .accept_o(uart_rd_w),
+
+ // Out
+ .pop_i(rx_accept_w),
+ .data_out_o(rx_data_w),
+ .valid_o(rx_valid_w)
+);
+
+//-----------------------------------------------------------------
+// States
+//-----------------------------------------------------------------
+reg [`STATE_R] state_q;
+reg [`STATE_R] next_state_r;
+
+always @ *
+begin
+ next_state_r = state_q;
+
+ case (next_state_r)
+ //-------------------------------------------------------------
+ // IDLE:
+ //-------------------------------------------------------------
+ STATE_IDLE:
+ begin
+ if (rx_valid_w)
+ begin
+ case (rx_data_w)
+ REQ_WRITE,
+ REQ_READ:
+ next_state_r = STATE_LEN;
+ default:
+ ;
+ endcase
+ end
+ end
+ //-----------------------------------------
+ // STATE_LEN
+ //-----------------------------------------
+ STATE_LEN :
+ begin
+ if (rx_valid_w)
+ next_state_r = STATE_ADDR0;
+ end
+ //-----------------------------------------
+ // STATE_ADDR
+ //-----------------------------------------
+ STATE_ADDR0 : if (rx_valid_w) next_state_r = STATE_ADDR1;
+ STATE_ADDR1 : if (rx_valid_w) next_state_r = STATE_ADDR2;
+ STATE_ADDR2 : if (rx_valid_w) next_state_r = STATE_ADDR3;
+ STATE_ADDR3 :
+ begin
+ if (rx_valid_w && mem_wr_q)
+ next_state_r = STATE_WRITE;
+ else if (rx_valid_w)
+ next_state_r = STATE_READ;
+ end
+ //-----------------------------------------
+ // STATE_WRITE
+ //-----------------------------------------
+ STATE_WRITE :
+ begin
+ if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
+ next_state_r = STATE_IDLE;
+ else
+ next_state_r = STATE_WRITE;
+ end
+ //-----------------------------------------
+ // STATE_READ
+ //-----------------------------------------
+ STATE_READ :
+ begin
+ // Data ready
+ if (mem_rvalid_i || magic_addr_w)
+ next_state_r = STATE_DATA0;
+ end
+ //-----------------------------------------
+ // STATE_DATA
+ //-----------------------------------------
+ STATE_DATA0 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA1;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA1;
+ end
+ STATE_DATA1 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA2;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA2;
+ end
+ STATE_DATA2 :
+ begin
+ if (read_skip_w)
+ next_state_r = STATE_DATA3;
+ else if (tx_accept_w && (len_q == 8'b0))
+ next_state_r = STATE_IDLE;
+ else if (tx_accept_w)
+ next_state_r = STATE_DATA3;
+ end
+ STATE_DATA3 :
+ begin
+ if (tx_accept_w && (len_q != 8'b0))
+ next_state_r = STATE_READ;
+ else if (tx_accept_w)
+ next_state_r = STATE_IDLE;
+ end
+ default:
+ ;
+ endcase
+end
+
+// State storage
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_IDLE;
+else
+ state_q <= next_state_r;
+
+//-----------------------------------------------------------------
+// RD/WR to and from UART
+//-----------------------------------------------------------------
+
+// Write to UART Tx buffer in the following states
+assign tx_valid_w = ((state_q == STATE_DATA0) |
+ (state_q == STATE_DATA1) |
+ (state_q == STATE_DATA2) |
+ (state_q == STATE_DATA3)) && !read_skip_w;
+
+// Accept data in the following states
+assign rx_accept_w = (state_q == STATE_IDLE) |
+ (state_q == STATE_LEN) |
+ (state_q == STATE_ADDR0) |
+ (state_q == STATE_ADDR1) |
+ (state_q == STATE_ADDR2) |
+ (state_q == STATE_ADDR3) |
+ (state_q == STATE_WRITE && !mem_busy_q);
+
+//-----------------------------------------------------------------
+// Capture length
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ len_q <= 8'd0;
+else if (state_q == STATE_LEN && rx_valid_w)
+ len_q[7:0] <= rx_data_w;
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+ len_q <= len_q - 8'd1;
+else if (state_q == STATE_READ && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
+ len_q <= len_q - 8'd1;
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w && !read_skip_w))
+ len_q <= len_q - 8'd1;
+
+//-----------------------------------------------------------------
+// Capture addr
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_addr_q <= 'd0;
+else if (state_q == STATE_ADDR0 && rx_valid_w)
+ mem_addr_q[31:24] <= rx_data_w;
+else if (state_q == STATE_ADDR1 && rx_valid_w)
+ mem_addr_q[23:16] <= rx_data_w;
+else if (state_q == STATE_ADDR2 && rx_valid_w)
+ mem_addr_q[15:8] <= rx_data_w;
+else if (state_q == STATE_ADDR3 && rx_valid_w)
+ mem_addr_q[7:0] <= rx_data_w;
+// Address increment on every access issued
+else if (state_q == STATE_WRITE && (mem_busy_q && mem_bvalid_i))
+ mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
+else if (state_q == STATE_READ && (mem_busy_q && mem_rvalid_i))
+ mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
+
+//-----------------------------------------------------------------
+// Data Index
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_idx_q <= 2'b0;
+else if (state_q == STATE_ADDR3)
+ data_idx_q <= rx_data_w[1:0];
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+ data_idx_q <= data_idx_q + 2'd1;
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && tx_accept_w && (data_idx_q != 2'b0))
+ data_idx_q <= data_idx_q - 2'd1;
+
+assign read_skip_w = (data_idx_q != 2'b0);
+
+//-----------------------------------------------------------------
+// Data Sample
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_q <= 32'b0;
+// Write to memory
+else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
+begin
+ case (data_idx_q)
+ 2'd0: data_q[7:0] <= rx_data_w;
+ 2'd1: data_q[15:8] <= rx_data_w;
+ 2'd2: data_q[23:16] <= rx_data_w;
+ 2'd3: data_q[31:24] <= rx_data_w;
+ endcase
+end
+// Read from GPIO Input?
+else if (state_q == STATE_READ && mem_addr_q == GPIO_ADDRESS)
+begin
+ data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
+end
+// Read from status register?
+else if (state_q == STATE_READ && mem_addr_q == STS_ADDRESS)
+ data_q <= {16'hcafe, 15'd0, mem_busy_q};
+// Read from memory
+else if (state_q == STATE_READ && mem_rvalid_i)
+ data_q <= mem_rdata_i;
+// Shift data out (read response -> UART)
+else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w || read_skip_w))
+ data_q <= {8'b0, data_q[31:8]};
+
+assign tx_data_w = data_q[7:0];
+
+assign mem_wdata_o = data_q;
+
+//-----------------------------------------------------------------
+// AXI: Write Request
+//-----------------------------------------------------------------
+reg mem_awvalid_q;
+reg mem_awvalid_r;
+
+reg mem_wvalid_q;
+reg mem_wvalid_r;
+
+always @ *
+begin
+ mem_awvalid_r = 1'b0;
+ mem_wvalid_r = 1'b0;
+
+ // Hold
+ if (mem_awvalid_o && !mem_awready_i)
+ mem_awvalid_r = mem_awvalid_q;
+ else if (mem_awvalid_o)
+ mem_awvalid_r = 1'b0;
+ // Every 4th byte, issue bus access
+ else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ mem_awvalid_r = !magic_addr_w;
+
+ // Hold
+ if (mem_wvalid_o && !mem_wready_i)
+ mem_wvalid_r = mem_wvalid_q;
+ else if (mem_wvalid_o)
+ mem_wvalid_r = 1'b0;
+ // Every 4th byte, issue bus access
+ else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ mem_wvalid_r = !magic_addr_w;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ mem_awvalid_q <= 1'b0;
+ mem_wvalid_q <= 1'b0;
+end
+else
+begin
+ mem_awvalid_q <= mem_awvalid_r;
+ mem_wvalid_q <= mem_wvalid_r;
+end
+
+assign mem_awvalid_o = mem_awvalid_q;
+assign mem_wvalid_o = mem_wvalid_q;
+assign mem_awaddr_o = {mem_addr_q[31:2], 2'b0};
+assign mem_awid_o = AXI_ID;
+assign mem_awlen_o = 8'b0;
+assign mem_awburst_o = 2'b01;
+assign mem_wlast_o = 1'b1;
+
+assign mem_bready_o = 1'b1;
+
+//-----------------------------------------------------------------
+// AXI: Read Request
+//-----------------------------------------------------------------
+reg mem_arvalid_q;
+reg mem_arvalid_r;
+
+always @ *
+begin
+ mem_arvalid_r = 1'b0;
+
+ // Hold
+ if (mem_arvalid_o && !mem_arready_i)
+ mem_arvalid_r = mem_arvalid_q;
+ else if (mem_arvalid_o)
+ mem_arvalid_r = 1'b0;
+ else if (state_q == STATE_READ && !mem_busy_q)
+ mem_arvalid_r = !magic_addr_w;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_arvalid_q <= 1'b0;
+else
+ mem_arvalid_q <= mem_arvalid_r;
+
+assign mem_arvalid_o = mem_arvalid_q;
+assign mem_araddr_o = {mem_addr_q[31:2], 2'b0};
+assign mem_arid_o = AXI_ID;
+assign mem_arlen_o = 8'b0;
+assign mem_arburst_o = 2'b01;
+
+assign mem_rready_o = 1'b1;
+
+//-----------------------------------------------------------------
+// Write mask
+//-----------------------------------------------------------------
+reg [3:0] mem_sel_q;
+reg [3:0] mem_sel_r;
+
+always @ *
+begin
+ mem_sel_r = 4'b1111;
+
+ case (data_idx_q)
+ 2'd0: mem_sel_r = 4'b0001;
+ 2'd1: mem_sel_r = 4'b0011;
+ 2'd2: mem_sel_r = 4'b0111;
+ 2'd3: mem_sel_r = 4'b1111;
+ endcase
+
+ case (mem_addr_q[1:0])
+ 2'd0: mem_sel_r = mem_sel_r & 4'b1111;
+ 2'd1: mem_sel_r = mem_sel_r & 4'b1110;
+ 2'd2: mem_sel_r = mem_sel_r & 4'b1100;
+ 2'd3: mem_sel_r = mem_sel_r & 4'b1000;
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_sel_q <= 4'b0;
+// Idle - reset for read requests
+else if (state_q == STATE_IDLE)
+ mem_sel_q <= 4'b1111;
+// Every 4th byte, issue bus access
+else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
+ mem_sel_q <= mem_sel_r;
+
+assign mem_wstrb_o = mem_sel_q;
+
+//-----------------------------------------------------------------
+// Write enable
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ mem_wr_q <= 1'b0;
+else if (state_q == STATE_IDLE && rx_valid_w)
+ mem_wr_q <= (rx_data_w == REQ_WRITE);
+
+//-----------------------------------------------------------------
+// Access in progress
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i == 1'b1)
+ mem_busy_q <= 1'b0;
+else if (mem_arvalid_o || mem_awvalid_o)
+ mem_busy_q <= 1'b1;
+else if (mem_bvalid_i || mem_rvalid_i)
+ mem_busy_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// GPIO Outputs
+//-----------------------------------------------------------------
+reg gpio_wr_q;
+reg [31:0] gpio_output_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ gpio_wr_q <= 1'b0;
+else if (mem_addr_q == GPIO_ADDRESS && state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
+ gpio_wr_q <= 1'b1;
+else
+ gpio_wr_q <= 1'b0;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ gpio_output_q <= 32'h0;
+else if (gpio_wr_q)
+ gpio_output_q <= data_q[31:0];
+
+assign gpio_outputs_o = gpio_output_q;
+
+
+
+endmodule
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..8f436397a3a194eb53fd294b079fc875d7356def
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
@@ -0,0 +1,118 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+module dbg_bridge_fifo
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter WIDTH = 8,
+ parameter DEPTH = 4,
+ parameter ADDR_W = 2
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input [WIDTH-1:0] data_in_i
+ ,input push_i
+ ,input pop_i
+
+ // Outputs
+ ,output [WIDTH-1:0] data_out_o
+ ,output accept_o
+ ,output valid_o
+);
+
+//-----------------------------------------------------------------
+// Local Params
+//-----------------------------------------------------------------
+localparam COUNT_W = ADDR_W + 1;
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [WIDTH-1:0] ram_q[DEPTH-1:0];
+reg [ADDR_W-1:0] rd_ptr_q;
+reg [ADDR_W-1:0] wr_ptr_q;
+reg [COUNT_W-1:0] count_q;
+
+//-----------------------------------------------------------------
+// Sequential
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ count_q <= {(COUNT_W) {1'b0}};
+ rd_ptr_q <= {(ADDR_W) {1'b0}};
+ wr_ptr_q <= {(ADDR_W) {1'b0}};
+end
+else
+begin
+ // Push
+ if (push_i & accept_o)
+ begin
+ ram_q[wr_ptr_q] <= data_in_i;
+ wr_ptr_q <= wr_ptr_q + 1;
+ end
+
+ // Pop
+ if (pop_i & valid_o)
+ rd_ptr_q <= rd_ptr_q + 1;
+
+ // Count up
+ if ((push_i & accept_o) & ~(pop_i & valid_o))
+ count_q <= count_q + 1;
+ // Count down
+ else if (~(push_i & accept_o) & (pop_i & valid_o))
+ count_q <= count_q - 1;
+end
+
+//-------------------------------------------------------------------
+// Combinatorial
+//-------------------------------------------------------------------
+/* verilator lint_off WIDTH */
+assign valid_o = (count_q != 0);
+assign accept_o = (count_q != DEPTH);
+/* verilator lint_on WIDTH */
+
+assign data_out_o = ram_q[rd_ptr_q];
+
+endmodule
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
new file mode 100644
index 0000000000000000000000000000000000000000..fc3c5709b45d95e0ddef7daddb2fec0bf5ad4286
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
@@ -0,0 +1,341 @@
+//-----------------------------------------------------------------
+// UART -> AXI Debug Bridge
+// V1.0
+// Ultra-Embedded.com
+// Copyright 2017-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+module dbg_bridge_uart
+
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+ parameter UART_DIVISOR_W = 9
+)
+
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+ // Clock & Reset
+ input clk_i,
+ input rst_i,
+
+ // Control
+ input [UART_DIVISOR_W-1:0] bit_div_i,
+ input stop_bits_i, // 0 = 1, 1 = 2
+
+ // Transmit
+ input wr_i,
+ input [7:0] data_i,
+ output tx_busy_o,
+
+ // Receive
+ input rd_i,
+ output [7:0] data_o,
+ output rx_ready_o,
+
+ output rx_err_o,
+
+ // UART pins
+ input rxd_i,
+ output txd_o
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+localparam START_BIT = 4'd0;
+localparam STOP_BIT0 = 4'd9;
+localparam STOP_BIT1 = 4'd10;
+
+// Xilinx placement pragmas:
+//synthesis attribute IOB of txd_q is "TRUE"
+
+// TX Signals
+reg tx_busy_q;
+reg [3:0] tx_bits_q;
+reg [UART_DIVISOR_W-1:0] tx_count_q;
+reg [7:0] tx_shift_reg_q;
+reg txd_q;
+
+// RX Signals
+reg rxd_q;
+reg [7:0] rx_data_q;
+reg [3:0] rx_bits_q;
+reg [UART_DIVISOR_W-1:0] rx_count_q;
+reg [7:0] rx_shift_reg_q;
+reg rx_ready_q;
+reg rx_busy_q;
+
+reg rx_err_q;
+
+//-----------------------------------------------------------------
+// Re-sync RXD
+//-----------------------------------------------------------------
+reg rxd_ms_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rxd_ms_q <= 1'b1;
+ rxd_q <= 1'b1;
+end
+else
+begin
+ rxd_ms_q <= rxd_i;
+ rxd_q <= rxd_ms_q;
+end
+
+//-----------------------------------------------------------------
+// RX Clock Divider
+//-----------------------------------------------------------------
+wire rx_sample_w = (rx_count_q == {(UART_DIVISOR_W){1'b0}});
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_count_q <= {(UART_DIVISOR_W){1'b0}};
+else
+begin
+ // Inactive
+ if (!rx_busy_q)
+ rx_count_q <= {1'b0, bit_div_i[UART_DIVISOR_W-1:1]};
+ // Rx bit timer
+ else if (rx_count_q != 0)
+ rx_count_q <= (rx_count_q - 1);
+ // Active
+ else if (rx_sample_w)
+ begin
+ // Last bit?
+ if ((rx_bits_q == STOP_BIT0 && !stop_bits_i) || (rx_bits_q == STOP_BIT1 && stop_bits_i))
+ rx_count_q <= {(UART_DIVISOR_W){1'b0}};
+ else
+ rx_count_q <= bit_div_i;
+ end
+end
+
+//-----------------------------------------------------------------
+// RX Shift Register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rx_shift_reg_q <= 8'h00;
+ rx_busy_q <= 1'b0;
+end
+// Rx busy
+else if (rx_busy_q && rx_sample_w)
+begin
+ // Last bit?
+ if (rx_bits_q == STOP_BIT0 && !stop_bits_i)
+ rx_busy_q <= 1'b0;
+ else if (rx_bits_q == STOP_BIT1 && stop_bits_i)
+ rx_busy_q <= 1'b0;
+ else if (rx_bits_q == START_BIT)
+ begin
+ // Start bit should still be low as sampling mid
+ // way through start bit, so if high, error!
+ if (rxd_q)
+ rx_busy_q <= 1'b0;
+ end
+ // Rx shift register
+ else
+ rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
+end
+// Start bit?
+else if (!rx_busy_q && rxd_q == 1'b0)
+begin
+ rx_shift_reg_q <= 8'h00;
+ rx_busy_q <= 1'b1;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_bits_q <= START_BIT;
+else if (rx_sample_w && rx_busy_q)
+begin
+ if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
+ rx_bits_q <= START_BIT;
+ else
+ rx_bits_q <= rx_bits_q + 4'd1;
+end
+else if (!rx_busy_q && (bit_div_i == {(UART_DIVISOR_W){1'b0}}))
+ rx_bits_q <= START_BIT + 4'd1;
+else if (!rx_busy_q)
+ rx_bits_q <= START_BIT;
+
+//-----------------------------------------------------------------
+// RX Data
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ rx_ready_q <= 1'b0;
+ rx_data_q <= 8'h00;
+ rx_err_q <= 1'b0;
+end
+else
+begin
+ // If reading data, reset data state
+ if (rd_i == 1'b1)
+ begin
+ rx_ready_q <= 1'b0;
+ rx_err_q <= 1'b0;
+ end
+
+ if (rx_busy_q && rx_sample_w)
+ begin
+ // Stop bit
+ if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
+ begin
+ // RXD should be still high
+ if (rxd_q)
+ begin
+ rx_data_q <= rx_shift_reg_q;
+ rx_ready_q <= 1'b1;
+ end
+ // Bad Stop bit - wait for a full bit period
+ // before allowing start bit detection again
+ else
+ begin
+ rx_ready_q <= 1'b0;
+ rx_data_q <= 8'h00;
+ rx_err_q <= 1'b1;
+ end
+ end
+ // Mid start bit sample - if high then error
+ else if (rx_bits_q == START_BIT && rxd_q)
+ rx_err_q <= 1'b1;
+ end
+end
+
+//-----------------------------------------------------------------
+// TX Clock Divider
+//-----------------------------------------------------------------
+wire tx_sample_w = (tx_count_q == {(UART_DIVISOR_W){1'b0}});
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ tx_count_q <= {(UART_DIVISOR_W){1'b0}};
+else
+begin
+ // Idle
+ if (!tx_busy_q)
+ tx_count_q <= bit_div_i;
+ // Tx bit timer
+ else if (tx_count_q != 0)
+ tx_count_q <= (tx_count_q - 1);
+ else if (tx_sample_w)
+ tx_count_q <= bit_div_i;
+end
+
+//-----------------------------------------------------------------
+// TX Shift Register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ tx_shift_reg_q <= 8'h00;
+ tx_busy_q <= 1'b0;
+end
+// Tx busy
+else if (tx_busy_q)
+begin
+ // Shift tx data
+ if (tx_bits_q != START_BIT && tx_sample_w)
+ tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};
+
+ // Last bit?
+ if (tx_bits_q == STOP_BIT0 && tx_sample_w && !stop_bits_i)
+ tx_busy_q <= 1'b0;
+ else if (tx_bits_q == STOP_BIT1 && tx_sample_w && stop_bits_i)
+ tx_busy_q <= 1'b0;
+end
+// Buffer data to transmit
+else if (wr_i)
+begin
+ tx_shift_reg_q <= data_i;
+ tx_busy_q <= 1'b1;
+end
+
+always @ (posedge clk_i or posedge rst_i )
+if (rst_i)
+ tx_bits_q <= 4'd0;
+else if (tx_sample_w && tx_busy_q)
+begin
+ if ((tx_bits_q == STOP_BIT1 && stop_bits_i) || (tx_bits_q == STOP_BIT0 && !stop_bits_i))
+ tx_bits_q <= START_BIT;
+ else
+ tx_bits_q <= tx_bits_q + 4'd1;
+end
+
+//-----------------------------------------------------------------
+// UART Tx Pin
+//-----------------------------------------------------------------
+reg txd_r;
+
+always @ *
+begin
+ txd_r = 1'b1;
+
+ if (tx_busy_q)
+ begin
+ // Start bit (TXD = L)
+ if (tx_bits_q == START_BIT)
+ txd_r = 1'b0;
+ // Stop bits (TXD = H)
+ else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
+ txd_r = 1'b1;
+ // Data bits
+ else
+ txd_r = tx_shift_reg_q[0];
+ end
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ txd_q <= 1'b1;
+else
+ txd_q <= txd_r;
+
+//-----------------------------------------------------------------
+// Outputs
+//-----------------------------------------------------------------
+assign tx_busy_o = tx_busy_q;
+assign rx_ready_o = rx_ready_q;
+assign txd_o = txd_q;
+assign data_o = rx_data_q;
+assign rx_err_o = rx_err_q;
+
+endmodule
diff --git a/socket/xilinx_lib/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl b/socket/xilinx_lib/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5460b99c29d7373d613a95000fe19b5dbf744753
--- /dev/null
+++ b/socket/xilinx_lib/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
@@ -0,0 +1,190 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_M00_AXI_TARGET_SLAVE_BASE_ADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_BURST_LEN" -parent ${Page_0} -widget comboBox
+ ipgui::add_param $IPINST -name "C_M00_AXI_ID_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
+ ipgui::add_param $IPINST -name "C_M00_AXI_AWUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_ARUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_WUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_RUSER_WIDTH" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_M00_AXI_BUSER_WIDTH" -parent ${Page_0}
+
+ ipgui::add_param $IPINST -name "CLK_SPEED"
+ ipgui::add_param $IPINST -name "UART_BAUD_RATE"
+
+}
+
+proc update_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to update CLK_SPEED when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to validate CLK_SPEED
+ return true
+}
+
+proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to validate UART_BAUD_RATE
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to update C_M00_AXI_TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to validate C_M00_AXI_TARGET_SLAVE_BASE_ADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to update C_M00_AXI_BURST_LEN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to validate C_M00_AXI_BURST_LEN
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to update C_M00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ID_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_M00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_AWUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ARUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_WUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_RUSER_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to update C_M00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to validate C_M00_AXI_BUSER_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_BURST_LEN { MODELPARAM_VALUE.C_M00_AXI_BURST_LEN PARAM_VALUE.C_M00_AXI_BURST_LEN } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BURST_LEN}] ${MODELPARAM_VALUE.C_M00_AXI_BURST_LEN}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.CLK_SPEED { MODELPARAM_VALUE.CLK_SPEED PARAM_VALUE.CLK_SPEED } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.CLK_SPEED}] ${MODELPARAM_VALUE.CLK_SPEED}
+}
+
+proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
+}
+