build_fpga.tcl

###-----------------------------------------------------------------------------
### Build FPGA Script
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
###
### David Mapstone (d.a.mapstone@soton.ac.uk)
###
### Copyright  2023, SoC Labs (www.soclabs.org)
###-----------------------------------------------------------------------------
#
# Developed & Tested using vivado_version 2021.1
#

# Get Environmnet Variables from Makefile
set fpga_name $env(FPGA_NAME)
set xilinx_part $env(FPGA_PART)
set import_dir $env(FPGA_TARGET)
set project_dir $env(FPGA_PROJECT_DIR)

set socket_lib $env(FPGA_SOCKET_LIB)
set nanosoc_lib $env(FPGA_NANOSOC_LIB)
set pynq_dir $env(FPGA_IMP_DIR)/pynq/$fpga_name/pynq/overlays/soclabs

#
# STEP#0: Build NanoSoC Design (without pads) as an "IP" library component for the testbench (in nanosoc_lib)
#
source build_nanosoc.tcl

#
# STEP#1: setup design sources and constraints
#
set_part $xilinx_part
set_property TARGET_LANGUAGE Verilog [current_project]
set_property DEFAULT_LIB work [current_project]

set paths [list \
 $socket_lib\
 $nanosoc_lib\
 ]

# Set IP repository paths
set obj [get_filesets sources_1]
if { $obj != {} } {
   set_property "ip_repo_paths" "[file normalize $socket_lib] [file normalize $nanosoc_lib]" $obj
   # Rebuild user ip_repo's index before adding any source files
   update_ip_catalog -rebuild
}

report_ip_status

# #
# # STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
# #
# # using script written out from GUI capture

create_bd_design design_1

read_verilog $import_dir/design_1_wrapper.v
source $import_dir/design_1.tcl
create_root_design ""


add_files $import_dir/fpga_pinmap.xdc

set_property top design_1_wrapper [current_fileset]

# #
# # STEP#3: save in Project mode to complete flow
# #
save_project_as $fpga_name $project_dir -exclude_run_results -force

update_compile_order -fileset sources_1

# #
# # STEP#4: synthesize project
# #
set_property part $xilinx_part [get_runs synth_1]
launch_runs synth_1 -jobs 8

wait_on_run synth_1

# #
# # STEP#5: place and route project
# #
set_property part $xilinx_part [get_runs impl_1]
launch_runs impl_1 -to_step write_bitstream -jobs 8

wait_on_run impl_1

# #
# # STEP#6: export design_1.bit and design_1.hwh files for PYNQ
# #

# write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa

# exec unzip -u -o $project/design_1.xsa -d $project/export
# exec mkdir -p $pynqDir
# exec cp -p $project/export/design_1.bit $pynqDir
# exec cp -p $project/export/design_1.hwh $pynqDir

# #exec rm -Rf vivado/

# exit 1