STarting Refactoring FPGA flow

fpga_imp/scripts/flist_to_tcl.py

makefile

socket/xilinx_lib/ADPcontrol_1.0/bd/bd.tcl

socket/xilinx_lib/ADPcontrol_1.0/component.xml

socket/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v

...et/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v

...et/xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v

.../xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v

.../xilinx_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v

...nx_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip

socket/xilinx_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v

socket/xilinx_lib/ADPcontrol_1.0/src/ADPmanager.v

socket/xilinx_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl

socket/xilinx_lib/axi_stream_io_1.0/bd/bd.tcl

socket/xilinx_lib/axi_stream_io_1.0/component.xml

..._io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd

..._io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl

...axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile

...eam_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c

...eam_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h