SOC1-167: WIP: Restructured verilog file to seperate rtl into groups

.gitignore

@@ -2,16 +2,14 @@
 
 # Exclude Compiled Binaries
 /software/*/*.elf
+/software/*/*.ELF
 /software/*/*.hex
 /software/*/*.lst
 /software/*/*.o
 
-/systems/mcu/testcodes/*.elf
-/systems/mcu/testcodes/*.hex
-/systems/mcu/testcodes/*.lst
-/systems/mcu/testcodes/*.o
-
-/systems/mcu/rtl_sim/*
-!/systems/mcu/rtl_sim/*.cmd
-!/systems/mcu/rtl_sim/makefile
-!/systems/mcu/rtl_sim/*.py
+# Compile Test Code Removal
+/systems/mcu/testcodes/*/*.elf
+/systems/mcu/testcodes/*/*.ELF
+/systems/mcu/testcodes/*/*.hex
+/systems/mcu/testcodes/*/*.lst
+/systems/mcu/testcodes/*/*.o

systems/mcu/rtl_sim/makefile → systems/mcu/makefile

 #-----------------------------------------------------------------------------
-# customised simulation makefile
+# NanoSoC Simulation Makefile 
 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 #
 # Contributors
@@ -44,7 +44,6 @@ NANOSOC_SW_DIR      ?= $(NANOSOC_TECH_DIR)/software
 NANOSOC_MCU_DIR := $(NANOSOC_SYSTEMS_DIR)/mcu
 VERILOG_DIR     := $(NANOSOC_MCU_DIR)/verilog
 TESTCODES_DIR   := $(NANOSOC_MCU_DIR)/testcodes
-RTL_SIM_DIR     := $(NANOSOC_MCU_DIR)/rtl_sim
 
 # Name of test directory (e.g. hello, dhry)
 # TESTNAME must be specified on the make command line
@@ -71,8 +70,8 @@ DEFINES_VC  += +define+CORTEX_M0 +define+USE_TARMAC
 TBENCH_VC   ?= -f $(PROJECT_DIR)/flist/project/system.flist
 
 #ADP command File
-# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd
-ADP_FILE ?= $(PROJECT_DIR)/system/stimulus/adp_hash_stim.cmd
+# Defaultly set to demo adp command file
+ADP_FILE ?= $(TESTCODES_DIR)/adp_demo/adp.cmd
 ADP_PATH := $(shell realpath $(ADP_FILE))
 ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
 
@@ -174,11 +173,11 @@ compile_xm :
 
 # Run simulation in batch mode
 run_xm : code compile_xm
-	@if [ ! -d logs ] ; then \
+	@if [ ! -d $(SIM_DIR)/logs ] ; then \
 	  mkdir $(SIM_DIR)/logs; \
 	fi
-	@echo run  >  run.tcl.tmp
-	@echo exit >> run.tcl.tmp
+	@echo run  >  $(SIM_DIR)/run.tcl.tmp
+	@echo exit >> $(SIM_DIR)/run.tcl.tmp
 	@mv  $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
 	cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl  | tee logs/run_$(TESTNAME).log ;
 	# @make verify
@@ -193,15 +192,15 @@ all_xm : compile_xm bootrom debugtester
 	@if [ ! -d $(SIM_DIR)/logs ] ; then \
 	  mkdir $(SIM_DIR)/logs; \
 	fi
-	@echo run  >  run.tcl.tmp
-	@echo exit >> run.tcl.tmp
-	@mv  run.tcl.tmp run.tcl
+	@echo run  >  $(SIM_DIR)run.tcl.tmp
+	@echo exit >> $(SIM_DIR)run.tcl.tmp
+	@mv  $(SIM_DIR)run.tcl.tmp $(SIM_DIR)run.tcl
 	@echo Run tests ...
 	for thistest in $(TEST_LIST) ; do \
 	  echo $$thistest   ; \
 	  make testcode TESTNAME=$$thistest ;\
 	  if [ -e image.hex ] ; then \
-	    xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
+	    cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
 	  else \
 	    echo Cannot read image.hex ;\
 	    exit 1; \
@@ -261,13 +260,13 @@ code : testcode bootrom debugtester
 # Compile bootloader
 # Note : The use of ls after compile allows the computing server to sync up
 bootrom:
-	@(cd $(NANOSOC_MCU_DIR)/$(BOOTLOADER) ;\
+	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\
 	make all $(SW_MAKE_OPTIONS) ;\
 	echo Compile done ;\
 	ls > /dev/null ;\
 	echo Copy $(BOOTLOADER).hex ;\
 	if [ -e  $(BOOTLOADER).hex ] ; then \
-	  cp $(BOOTLOADER).hex  $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
+	  cp $(BOOTLOADER).hex  $(SIM_DIR)/$(BOOTLOADER).hex ;\
 	else \
 	  while [ ! -e $(BOOTLOADER).hex ] ; do \
 	    echo Wait for hex file ...; \
@@ -275,14 +274,14 @@ bootrom:
 	    sleep 5; \
 	  done; \
 	  if [ -e  $(BOOTLOADER).hex ] ; then \
-	    cp $(BOOTLOADER).hex  $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
+	    cp $(BOOTLOADER).hex  $(SIM_DIR)/$(BOOTLOADER).hex ;\
 	  else \
 	    echo Problem reading hex file ;\
 	    exit 1; \
 	  fi ;\
 	fi ;\
-	cp $(BOOTLOADER).hex  $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
-	cd $(RTL_SIM_DIR) )
+	cp $(BOOTLOADER).hex  $(SIM_DIR)/$(BOOTLOADER).hex ;\
+	cd $(SIM_DIR) )
 
 # Compile test code
 # Note : The use of ls after compile allows the computing server to sync up
@@ -297,7 +296,7 @@ endif
 	  ls > /dev/null ;\
 	  echo Copy $(TESTNAME).hex ;\
 	  if [ -e  $(TESTNAME).hex ] ; then \
-	    cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
+	    cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
 	  else \
 	    while [ ! -e $(TESTNAME).hex ] ; do \
 	      echo Wait for $(TESTNAME).hex file ...; \
@@ -305,13 +304,13 @@ endif
 	      sleep 5 ; \
 	    done; \
 	    if [ -e  $(TESTNAME).hex ] ; then \
-	      cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
+	      cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
 	    else \
 	      echo Problem reading hex file ;\
 	      exit 1; \
 	    fi ;\
 	  fi ;\
-	  cd $(RTL_SIM_DIR) ;\
+	  cd $(SIM_DIR) ;\
 	else \
 	  echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\
 	  exit 1 ;\
@@ -328,7 +327,7 @@ debugtester:
 	ls > /dev/null ;\
 	echo Copy $(DEBUGTESTER)_le.hex ;\
 	if [ -e  $(DEBUGTESTER)_le.hex ] ; then \
-	  cp $(DEBUGTESTER)_le.hex  $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+	  cp $(DEBUGTESTER)_le.hex  $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
 	else \
 	  while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \
 	    echo Wait for hex file ...; \
@@ -336,12 +335,12 @@ debugtester:
 	    sleep 5 ; \
 	  done; \
 	  if [ -e  $(DEBUGTESTER)_le.hex ] ; then \
-	    cp $(DEBUGTESTER)_le.hex  $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+	    cp $(DEBUGTESTER)_le.hex  $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
 	  fi ;\
 	fi ;\
 	echo Copy $(DEBUGTESTER)_be.hex ;\
 	if [ -e  $(DEBUGTESTER)_be.hex ] ; then \
-	  cp $(DEBUGTESTER)_be.hex  $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+	  cp $(DEBUGTESTER)_be.hex  $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
 	else \
 	  while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \
 	    echo Wait for hex file ...;\
@@ -349,14 +348,14 @@ debugtester:
 	    sleep 5 ; \
 	  done; \
 	  if [ -e  $(DEBUGTESTER)_be.hex ] ; then \
-	    cp $(DEBUGTESTER)_be.hex  $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+	    cp $(DEBUGTESTER)_be.hex  $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
 	  fi ;\
 	fi ;\
 	if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \
 	    echo Problem reading hex file ;\
 	    exit 1 ;\
 	fi ;\
-	cd $(RTL_SIM_DIR) )
+	cd $(SIM_DIR) )
 
 # Compile all software including boot ROM
 compile_all_code: bootrom debugtester
@@ -389,25 +388,25 @@ v2html:
 	rm *.html; rm *.gif; rm *.gz; \
 	~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
 	cp -p tb_nanosoc.v.html hierarchy.html ; \
-	cd $(RTL_SIM_DIR) ; )
+	cd $(SIM_DIR) ; )
 	gtar zcvf $(NANOSOC_MCU_DIR)/v2html_doc.tgz $(NANOSOC_MCU_DIR)/v2html_doc
 
 
 # Remove all software compilation results
 clean_all_code:
-	@(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(RTL_SIM_DIR); )
-	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
+	@(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(SIM_DIR); )
+	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(SIM_DIR); )
 	for thistest in $(TEST_LIST) ; do \
 	  echo Cleaning $$thistest ...  ; \
 	  cd $(TESTCODES_DIR)/$$thistest ; \
 	  make clean; \
-	  cd $(RTL_SIM_DIR); \
+	  cd $(SIM_DIR); \
 	done
 
 # Remove only bootloader and default selected test
 clean_code:
-	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
-	@(cd $(TESTCODES_DIR)/$(TESTNAME)   ; make clean; cd $(RTL_SIM_DIR); )
+	@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(SIM_DIR); )
+	@(cd $(TESTCODES_DIR)/$(TESTNAME)   ; make clean; cd $(SIM_DIR); )
 
 # ----- verification ------
 verify: