diff --git a/.gitignore b/.gitignore
index b950335ef70661320321f494994d84bcf309fc2b..1f0d18efffb892b16c38aa0c50656611a3a6f73b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,16 +2,14 @@
# Exclude Compiled Binaries
/software/*/*.elf
+/software/*/*.ELF
/software/*/*.hex
/software/*/*.lst
/software/*/*.o
-/systems/mcu/testcodes/*.elf
-/systems/mcu/testcodes/*.hex
-/systems/mcu/testcodes/*.lst
-/systems/mcu/testcodes/*.o
-
-/systems/mcu/rtl_sim/*
-!/systems/mcu/rtl_sim/*.cmd
-!/systems/mcu/rtl_sim/makefile
-!/systems/mcu/rtl_sim/*.py
+# Compile Test Code Removal
+/systems/mcu/testcodes/*/*.elf
+/systems/mcu/testcodes/*/*.ELF
+/systems/mcu/testcodes/*/*.hex
+/systems/mcu/testcodes/*/*.lst
+/systems/mcu/testcodes/*/*.o
diff --git a/systems/mcu/testcodes/aes128_tests/aes128.h b/systems/mcu/aes/aes128_tests/aes128.h
similarity index 100%
rename from systems/mcu/testcodes/aes128_tests/aes128.h
rename to systems/mcu/aes/aes128_tests/aes128.h
diff --git a/systems/mcu/testcodes/aes128_tests/aes128_tests.c b/systems/mcu/aes/aes128_tests/aes128_tests.c
similarity index 100%
rename from systems/mcu/testcodes/aes128_tests/aes128_tests.c
rename to systems/mcu/aes/aes128_tests/aes128_tests.c
diff --git a/systems/mcu/testcodes/aes128_tests/dma_pl230_driver.c b/systems/mcu/aes/aes128_tests/dma_pl230_driver.c
similarity index 100%
rename from systems/mcu/testcodes/aes128_tests/dma_pl230_driver.c
rename to systems/mcu/aes/aes128_tests/dma_pl230_driver.c
diff --git a/systems/mcu/testcodes/aes128_tests/dma_pl230_driver.h b/systems/mcu/aes/aes128_tests/dma_pl230_driver.h
similarity index 100%
rename from systems/mcu/testcodes/aes128_tests/dma_pl230_driver.h
rename to systems/mcu/aes/aes128_tests/dma_pl230_driver.h
diff --git a/systems/mcu/testcodes/aes128_tests/makefile b/systems/mcu/aes/aes128_tests/makefile
similarity index 100%
rename from systems/mcu/testcodes/aes128_tests/makefile
rename to systems/mcu/aes/aes128_tests/makefile
diff --git a/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v b/systems/mcu/aes/verilog/soclabs_ahb_aes128_ctrl.v
similarity index 100%
rename from systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v
rename to systems/mcu/aes/verilog/soclabs_ahb_aes128_ctrl.v
diff --git a/systems/mcu/verilog/pl230_defs.v b/systems/mcu/defines/pl230_defs.v
similarity index 100%
rename from systems/mcu/verilog/pl230_defs.v
rename to systems/mcu/defines/pl230_defs.v
diff --git a/systems/mcu/rtl_sim/makefile b/systems/mcu/makefile
similarity index 90%
rename from systems/mcu/rtl_sim/makefile
rename to systems/mcu/makefile
index 4216a3c8e024735bfcc28129ecbdceff29f42c75..fde6089f3274b4802e6374c7199c74d84007195d 100644
--- a/systems/mcu/rtl_sim/makefile
+++ b/systems/mcu/makefile
@@ -1,5 +1,5 @@
#-----------------------------------------------------------------------------
-# customised simulation makefile
+# NanoSoC Simulation Makefile
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
@@ -44,7 +44,6 @@ NANOSOC_SW_DIR ?= $(NANOSOC_TECH_DIR)/software
NANOSOC_MCU_DIR := $(NANOSOC_SYSTEMS_DIR)/mcu
VERILOG_DIR := $(NANOSOC_MCU_DIR)/verilog
TESTCODES_DIR := $(NANOSOC_MCU_DIR)/testcodes
-RTL_SIM_DIR := $(NANOSOC_MCU_DIR)/rtl_sim
# Name of test directory (e.g. hello, dhry)
# TESTNAME must be specified on the make command line
@@ -71,8 +70,8 @@ DEFINES_VC += +define+CORTEX_M0 +define+USE_TARMAC
TBENCH_VC ?= -f $(PROJECT_DIR)/flist/project/system.flist
#ADP command File
-# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd
-ADP_FILE ?= $(PROJECT_DIR)/system/stimulus/adp_hash_stim.cmd
+# Defaultly set to demo adp command file
+ADP_FILE ?= $(TESTCODES_DIR)/adp_demo/adp.cmd
ADP_PATH := $(shell realpath $(ADP_FILE))
ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
@@ -174,11 +173,11 @@ compile_xm :
# Run simulation in batch mode
run_xm : code compile_xm
- @if [ ! -d logs ] ; then \
+ @if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir $(SIM_DIR)/logs; \
fi
- @echo run > run.tcl.tmp
- @echo exit >> run.tcl.tmp
+ @echo run > $(SIM_DIR)/run.tcl.tmp
+ @echo exit >> $(SIM_DIR)/run.tcl.tmp
@mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
# @make verify
@@ -193,15 +192,15 @@ all_xm : compile_xm bootrom debugtester
@if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir $(SIM_DIR)/logs; \
fi
- @echo run > run.tcl.tmp
- @echo exit >> run.tcl.tmp
- @mv run.tcl.tmp run.tcl
+ @echo run > $(SIM_DIR)run.tcl.tmp
+ @echo exit >> $(SIM_DIR)run.tcl.tmp
+ @mv $(SIM_DIR)run.tcl.tmp $(SIM_DIR)run.tcl
@echo Run tests ...
for thistest in $(TEST_LIST) ; do \
echo $$thistest ; \
make testcode TESTNAME=$$thistest ;\
if [ -e image.hex ] ; then \
- xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
+ cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
else \
echo Cannot read image.hex ;\
exit 1; \
@@ -261,13 +260,13 @@ code : testcode bootrom debugtester
# Compile bootloader
# Note : The use of ls after compile allows the computing server to sync up
bootrom:
- @(cd $(NANOSOC_MCU_DIR)/$(BOOTLOADER) ;\
+ @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ;\
make all $(SW_MAKE_OPTIONS) ;\
echo Compile done ;\
ls > /dev/null ;\
echo Copy $(BOOTLOADER).hex ;\
if [ -e $(BOOTLOADER).hex ] ; then \
- cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
+ cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
else \
while [ ! -e $(BOOTLOADER).hex ] ; do \
echo Wait for hex file ...; \
@@ -275,14 +274,14 @@ bootrom:
sleep 5; \
done; \
if [ -e $(BOOTLOADER).hex ] ; then \
- cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
+ cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
else \
echo Problem reading hex file ;\
exit 1; \
fi ;\
fi ;\
- cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
- cd $(RTL_SIM_DIR) )
+ cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
+ cd $(SIM_DIR) )
# Compile test code
# Note : The use of ls after compile allows the computing server to sync up
@@ -297,7 +296,7 @@ endif
ls > /dev/null ;\
echo Copy $(TESTNAME).hex ;\
if [ -e $(TESTNAME).hex ] ; then \
- cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
+ cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
else \
while [ ! -e $(TESTNAME).hex ] ; do \
echo Wait for $(TESTNAME).hex file ...; \
@@ -305,13 +304,13 @@ endif
sleep 5 ; \
done; \
if [ -e $(TESTNAME).hex ] ; then \
- cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
+ cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
else \
echo Problem reading hex file ;\
exit 1; \
fi ;\
fi ;\
- cd $(RTL_SIM_DIR) ;\
+ cd $(SIM_DIR) ;\
else \
echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\
exit 1 ;\
@@ -328,7 +327,7 @@ debugtester:
ls > /dev/null ;\
echo Copy $(DEBUGTESTER)_le.hex ;\
if [ -e $(DEBUGTESTER)_le.hex ] ; then \
- cp $(DEBUGTESTER)_le.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+ cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
else \
while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \
echo Wait for hex file ...; \
@@ -336,12 +335,12 @@ debugtester:
sleep 5 ; \
done; \
if [ -e $(DEBUGTESTER)_le.hex ] ; then \
- cp $(DEBUGTESTER)_le.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
+ cp $(DEBUGTESTER)_le.hex $(SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
fi ;\
fi ;\
echo Copy $(DEBUGTESTER)_be.hex ;\
if [ -e $(DEBUGTESTER)_be.hex ] ; then \
- cp $(DEBUGTESTER)_be.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+ cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
else \
while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \
echo Wait for hex file ...;\
@@ -349,14 +348,14 @@ debugtester:
sleep 5 ; \
done; \
if [ -e $(DEBUGTESTER)_be.hex ] ; then \
- cp $(DEBUGTESTER)_be.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
+ cp $(DEBUGTESTER)_be.hex $(SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
fi ;\
fi ;\
if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \
echo Problem reading hex file ;\
exit 1 ;\
fi ;\
- cd $(RTL_SIM_DIR) )
+ cd $(SIM_DIR) )
# Compile all software including boot ROM
compile_all_code: bootrom debugtester
@@ -389,25 +388,25 @@ v2html:
rm *.html; rm *.gif; rm *.gz; \
~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
cp -p tb_nanosoc.v.html hierarchy.html ; \
- cd $(RTL_SIM_DIR) ; )
+ cd $(SIM_DIR) ; )
gtar zcvf $(NANOSOC_MCU_DIR)/v2html_doc.tgz $(NANOSOC_MCU_DIR)/v2html_doc
# Remove all software compilation results
clean_all_code:
- @(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(RTL_SIM_DIR); )
- @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
+ @(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(SIM_DIR); )
+ @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(SIM_DIR); )
for thistest in $(TEST_LIST) ; do \
echo Cleaning $$thistest ... ; \
cd $(TESTCODES_DIR)/$$thistest ; \
make clean; \
- cd $(RTL_SIM_DIR); \
+ cd $(SIM_DIR); \
done
# Remove only bootloader and default selected test
clean_code:
- @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
- @(cd $(TESTCODES_DIR)/$(TESTNAME) ; make clean; cd $(RTL_SIM_DIR); )
+ @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(SIM_DIR); )
+ @(cd $(TESTCODES_DIR)/$(TESTNAME) ; make clean; cd $(SIM_DIR); )
# ----- verification ------
verify:
diff --git a/systems/mcu/verilog/ahb_bootrom.v b/systems/mcu/src/bootrom/ahb_bootrom.v
similarity index 100%
rename from systems/mcu/verilog/ahb_bootrom.v
rename to systems/mcu/src/bootrom/ahb_bootrom.v
diff --git a/systems/mcu/verilog/bootrom.v b/systems/mcu/src/bootrom/bootrom.v
similarity index 100%
rename from systems/mcu/verilog/bootrom.v
rename to systems/mcu/src/bootrom/bootrom.v
diff --git a/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v b/systems/mcu/src/cmsdk_ahb_cs_rom_table.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
rename to systems/mcu/src/cmsdk_ahb_cs_rom_table.v
diff --git a/systems/mcu/verilog/cmsdk_apb_subsystem.v b/systems/mcu/src/cmsdk_apb_subsystem.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_apb_subsystem.v
rename to systems/mcu/src/cmsdk_apb_subsystem.v
diff --git a/systems/mcu/verilog/cmsdk_apb_usrt.v b/systems/mcu/src/cmsdk_apb_usrt.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_apb_usrt.v
rename to systems/mcu/src/cmsdk_apb_usrt.v
diff --git a/systems/mcu/verilog/cmsdk_clkreset.v b/systems/mcu/src/cmsdk_clkreset.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_clkreset.v
rename to systems/mcu/src/cmsdk_clkreset.v
diff --git a/systems/mcu/verilog/cmsdk_ft1248x1_adpio.v b/systems/mcu/src/cmsdk_ft1248x1_adpio.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_ft1248x1_adpio.v
rename to systems/mcu/src/cmsdk_ft1248x1_adpio.v
diff --git a/systems/mcu/verilog/cmsdk_mcu_clkctrl.v b/systems/mcu/src/cmsdk_mcu_clkctrl.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_mcu_clkctrl.v
rename to systems/mcu/src/cmsdk_mcu_clkctrl.v
diff --git a/systems/mcu/verilog/cmsdk_mcu_pin_mux.v b/systems/mcu/src/cmsdk_mcu_pin_mux.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_mcu_pin_mux.v
rename to systems/mcu/src/cmsdk_mcu_pin_mux.v
diff --git a/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v b/systems/mcu/src/cmsdk_mcu_stclkctrl.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
rename to systems/mcu/src/cmsdk_mcu_stclkctrl.v
diff --git a/systems/mcu/verilog/cmsdk_mcu_sysctrl.v b/systems/mcu/src/cmsdk_mcu_sysctrl.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_mcu_sysctrl.v
rename to systems/mcu/src/cmsdk_mcu_sysctrl.v
diff --git a/systems/mcu/verilog/cmsdk_uart_capture.v b/systems/mcu/src/cmsdk_uart_capture.v
similarity index 100%
rename from systems/mcu/verilog/cmsdk_uart_capture.v
rename to systems/mcu/src/cmsdk_uart_capture.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/README.txt b/systems/mcu/src/gen_ahb_busmatrix/README.txt
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/README.txt
rename to systems/mcu/src/gen_ahb_busmatrix/README.txt
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/bin/BuildBusMatrix.pl b/systems/mcu/src/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
rename to systems/mcu/src/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/bin/lib/xmlparser.pm b/systems/mcu/src/gen_ahb_busmatrix/bin/lib/xmlparser.pm
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/bin/lib/xmlparser.pm
rename to systems/mcu/src/gen_ahb_busmatrix/bin/lib/xmlparser.pm
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr b/systems/mcu/src/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
rename to systems/mcu/src/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml b/systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
rename to systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml b/systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
rename to systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml b/systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
rename to systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml b/systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
rename to systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log b/systems/mcu/src/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
rename to systems/mcu/src/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v b/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
rename to systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_full.xml b/systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_full.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_full.xml
rename to systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_full.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_sparse.xml b/systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_sparse.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/xml/example2x3_sparse.xml
rename to systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_sparse.xml
diff --git a/systems/mcu/verilog/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml b/systems/mcu/src/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
similarity index 100%
rename from systems/mcu/verilog/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
rename to systems/mcu/src/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
diff --git a/systems/mcu/verilog/nanosoc_chip.v b/systems/mcu/src/nanosoc_chip.v
similarity index 100%
rename from systems/mcu/verilog/nanosoc_chip.v
rename to systems/mcu/src/nanosoc_chip.v
diff --git a/systems/mcu/verilog/nanosoc_chip_pads.v b/systems/mcu/src/nanosoc_chip_pads.v
similarity index 100%
rename from systems/mcu/verilog/nanosoc_chip_pads.v
rename to systems/mcu/src/nanosoc_chip_pads.v
diff --git a/systems/mcu/verilog/nanosoc_cpu.v b/systems/mcu/src/nanosoc_cpu.v
similarity index 100%
rename from systems/mcu/verilog/nanosoc_cpu.v
rename to systems/mcu/src/nanosoc_cpu.v
diff --git a/systems/mcu/verilog/nanosoc_sys_ahb_decode.v b/systems/mcu/src/nanosoc_sys_ahb_decode.v
similarity index 100%
rename from systems/mcu/verilog/nanosoc_sys_ahb_decode.v
rename to systems/mcu/src/nanosoc_sys_ahb_decode.v
diff --git a/systems/mcu/verilog/nanosoc_sysio.v b/systems/mcu/src/nanosoc_sysio.v
similarity index 100%
rename from systems/mcu/verilog/nanosoc_sysio.v
rename to systems/mcu/src/nanosoc_sysio.v
diff --git a/systems/mcu/rtl_sim/adp.cmd b/systems/mcu/testcodes/adp_demo/adp.cmd
similarity index 100%
rename from systems/mcu/rtl_sim/adp.cmd
rename to systems/mcu/testcodes/adp_demo/adp.cmd
diff --git a/systems/mcu/testcodes/setup_ds5_tools.scr b/systems/mcu/testcodes/setup_ds5_tools.scr
deleted file mode 100644
index fa703ecf275a34a6d6a56e3751e5a9931deea1eb..0000000000000000000000000000000000000000
--- a/systems/mcu/testcodes/setup_ds5_tools.scr
+++ /dev/null
@@ -1,6 +0,0 @@
-export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
-export ARM_TOOL_VARIANT=gold
-export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
-
-
-
diff --git a/systems/mcu/tools/setup_ds5_tools.scr b/systems/mcu/tools/setup_ds5_tools.scr
deleted file mode 100644
index 477a508b4492fe00ad23b1b2bf82f6f5fefeecce..0000000000000000000000000000000000000000
--- a/systems/mcu/tools/setup_ds5_tools.scr
+++ /dev/null
@@ -1,3 +0,0 @@
-export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
-export ARM_TOOL_VARIANT=gold
-export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
diff --git a/systems/mcu/verilog/aes128_log_to_file.v b/systems/mcu/verif/aes128_log_to_file.v
similarity index 100%
rename from systems/mcu/verilog/aes128_log_to_file.v
rename to systems/mcu/verif/aes128_log_to_file.v
diff --git a/systems/mcu/verilog/axi_streamio8_buffer.v b/systems/mcu/verif/axi_stream_io_8_buffer.v
similarity index 97%
rename from systems/mcu/verilog/axi_streamio8_buffer.v
rename to systems/mcu/verif/axi_stream_io_8_buffer.v
index 8dab10347f5271d753c979cf97979bcab463ebf7..d44280a710518c32f5910e0801820d5b7892b867 100644
--- a/systems/mcu/verilog/axi_streamio8_buffer.v
+++ b/systems/mcu/verif/axi_stream_io_8_buffer.v
@@ -14,7 +14,7 @@
//-----------------------------------------------------------------------------
-module axi_streamio8_buffer
+module axi_stream_io_8_buffer
(
input wire aclk,
input wire aresetn,
diff --git a/systems/mcu/verilog/axi_streamio8_rxd_to_file.v b/systems/mcu/verif/axi_stream_io_8_rxd_to_file.v
similarity index 98%
rename from systems/mcu/verilog/axi_streamio8_rxd_to_file.v
rename to systems/mcu/verif/axi_stream_io_8_rxd_to_file.v
index 6ac805447ac71857d52383adfa02fdf1b7103f2a..33b169a5d6a58896af2400a0442562fa85734e19 100644
--- a/systems/mcu/verilog/axi_streamio8_rxd_to_file.v
+++ b/systems/mcu/verif/axi_stream_io_8_rxd_to_file.v
@@ -15,7 +15,7 @@
//-----------------------------------------------------------------------------
-module axi_streamio8_rxd_to_file
+module axi_stream_io_8_rxd_to_file
#(parameter RXDFILENAME = "rxd.log",
parameter VERBOSE = 0)
(
diff --git a/systems/mcu/verilog/axi_streamio8_txd_from_file.v b/systems/mcu/verif/axi_stream_io_8_txd_from_file.v
similarity index 98%
rename from systems/mcu/verilog/axi_streamio8_txd_from_file.v
rename to systems/mcu/verif/axi_stream_io_8_txd_from_file.v
index 7ec60d97014ff2963d6cdb9288d6e3a29efde983..46307a49f54eeb6321a864867cbd1f46c1278030 100644
--- a/systems/mcu/verilog/axi_streamio8_txd_from_file.v
+++ b/systems/mcu/verif/axi_stream_io_8_txd_from_file.v
@@ -15,7 +15,7 @@
//-----------------------------------------------------------------------------
-module axi_streamio8_txd_from_file
+module axi_stream_io_8_txd_from_file
#(parameter TXDFILENAME = "txd.cmd",
parameter VERBOSE = 0)
(
diff --git a/systems/mcu/verilog/dma_log_to_file.v b/systems/mcu/verif/dma_log_to_file.v
similarity index 100%
rename from systems/mcu/verilog/dma_log_to_file.v
rename to systems/mcu/verif/dma_log_to_file.v
diff --git a/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v b/systems/mcu/verif/ft1248x1_to_axi_streamio_v1_0.v
similarity index 100%
rename from systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v
rename to systems/mcu/verif/ft1248x1_to_axi_streamio_v1_0.v
diff --git a/systems/mcu/verilog/ft1248x1_track.v b/systems/mcu/verif/ft1248x1_track.v
similarity index 100%
rename from systems/mcu/verilog/ft1248x1_track.v
rename to systems/mcu/verif/ft1248x1_track.v
diff --git a/systems/mcu/verilog/tb_nanosoc.v b/systems/mcu/verif/tb_nanosoc.v
similarity index 99%
rename from systems/mcu/verilog/tb_nanosoc.v
rename to systems/mcu/verif/tb_nanosoc.v
index 6515d988f78d257eb4e6dee5afe9632b03cb86ab..56c848c3c9801973c9b5ac7bffda536f37ba1bc1 100644
--- a/systems/mcu/verilog/tb_nanosoc.v
+++ b/systems/mcu/verif/tb_nanosoc.v
@@ -266,9 +266,9 @@ wire rxd8_ready;
wire rxd8_valid;
wire [7:0] rxd8_data ;
-axi_streamio8_txd_from_file
+axi_stream_io_8_txd_from_file
#(.TXDFILENAME(ADP_FILENAME))
- u_axi_streamio8_txd_from_file
+ u_axi_stream_io_8_txd_from_file
(
.aclk (XTAL1),
.aresetn (NRST),
@@ -278,8 +278,8 @@ axi_streamio8_txd_from_file
);
/*
-axi_streamio8_buffer
- u_axi_streamio8_buffer
+axi_stream_io_8_buffer
+ u_axi_stream_io_8_buffer
(
.aclk (XTAL1),
.aresetn (NRST),
@@ -316,9 +316,9 @@ ft1248x1_to_axi_streamio_v1_0
.txd_tdata8_o (rxd8_data)
);
-axi_streamio8_rxd_to_file
+axi_stream_io_8_rxd_to_file
#(.RXDFILENAME("ft1248_out.log"))
- u_axi_streamio8_rxd_to_file
+ u_axi_stream_io_8_rxd_to_file
(
.aclk (XTAL1),
.aresetn (NRST),
diff --git a/systems/mcu/verilog/track_tb_iostream.v b/systems/mcu/verif/track_tb_iostream.v
similarity index 100%
rename from systems/mcu/verilog/track_tb_iostream.v
rename to systems/mcu/verif/track_tb_iostream.v
diff --git a/systems/mcu/verilog/tbench_M0.vc b/systems/mcu/verilog/tbench_M0.vc
deleted file mode 100644
index 07a2b2d9090916693aa49c099ab87c40e388c82e..0000000000000000000000000000000000000000
--- a/systems/mcu/verilog/tbench_M0.vc
+++ /dev/null
@@ -1,146 +0,0 @@
-//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: $
-//
-// Revision : $Revision: $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Cortex-M0 example system
-//-----------------------------------------------------------------------------
-//
-// ================= MCU System options ===============
-// Option to select Cortex-M0+ processor in example system
-+define+CORTEX_M0
-
-// =================== Tarmac Logging =================
-+define+USE_TARMAC
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ================= Top level file ===================
-../verilog/tb_nanosoc.v
-+incdir+../verilog
-+incdir+/../verilog/soclabs_4x7_AhbMatrix
--y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
-
-// ============= GLIB Generic Library path =============
-../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
-../../../../../GLIB/pads/verilog/PAD_VDDIO.v
-../../../../../GLIB/pads/verilog/PAD_VSSIO.v
-../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
-../../../../../GLIB/pads/verilog/PAD_VSS.v
-../../../../../GLIB/mem/verilog/SROM_Ax32.v
-../../../../../GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
-
-// ================= Testbench path ===================
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
-
-// ============= MCU Module search path =============
--y ../verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
-
-
-//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
-/// upgrade to AAA 'rel2' version
-+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
-../verilog/pl230_defs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
-
-../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
-../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
-../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
-../verilog/cmsdk_apb_usrt.v
-
-// ============= Cortex-M0 Module search path =============
-
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
-
-
-// ============= Cortex-M0 Include file search path =============
-
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
-
-
-
-// =============Debug tester Include file search path =============
-
-
-// ============= OVL support libraries =============
-//+define+ASSERT_ON
-//+define+OVL_ASSERT_ON
-//+define+ARM_ASSERT_ON
-//+define+ARM_AHB_ASSERT_ON
-//+define+ARM_APB_ASSERT_ON
-//+define+ARM_CMSDK_ASSERT_ON
-
-// ============= Verification components =============
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
-
-///+incdir+/arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
-///-y /arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
diff --git a/systems/mcu/verilog/v2html_M0.vc b/systems/mcu/verilog/v2html_M0.vc
deleted file mode 100644
index d744b3ebe1e9f793f1c49be09c55a6b515cf2faf..0000000000000000000000000000000000000000
--- a/systems/mcu/verilog/v2html_M0.vc
+++ /dev/null
@@ -1,121 +0,0 @@
-//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: $
-//
-// Revision : $Revision: $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Cortex-M0 example system
-//-----------------------------------------------------------------------------
-//
-// ================= MCU System options ===============
-// Option to select Cortex-M0+ processor in example system
-+define+CORTEX_M0
-
-// =================== Tarmac Logging =================
-+define+USE_TARMAC
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ================= Top level file ===================
-../verilog/tb_nanosoc.v
-+incdir+../verilog
-+incdir+/../verilog/soclabs_4x7_AhbMatrix
--y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
-
-// ================= Testbench path ===================
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
-
-// ============= GLIB Generic Library path =============
-../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
-../../../../../GLIB/pads/verilog/PAD_VDDIO.v
-../../../../../GLIB/pads/verilog/PAD_VSSIO.v
-../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
-../../../../../GLIB/pads/verilog/PAD_VSS.v
-../../../../../GLIB/mem/verilog/SROM_Ax32.v
-../../../../../GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
-
-// ============= IPLIB soclabs IP Library path =============
-../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
-../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
-../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
-../verilog/cmsdk_apb_usrt.v
-
-// ============= MCU Module search path =============
--y ../verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
--y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
-//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
-+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
-
-//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
-/// upgrade to AAA 'rel2' version
-+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
-../verilog/pl230_defs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
-
-// ============= Cortex-M0 Module search path =============
-// guts of core not exposed, periphery only
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
--y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
-
-// ============= Cortex-M0 Include file search path =============
-// guts of core not exposed, periphery only
-
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
-