Skip to content
Snippets Groups Projects
Commit 5146160b authored by dam1n19's avatar dam1n19
Browse files

SOC1-167: WIP: Restructured verilog file to seperate rtl into groups

parent 3ce4c66d
No related branches found
No related tags found
No related merge requests found
Showing with 9 additions and 285 deletions
export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
export ARM_TOOL_VARIANT=gold
export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
export ARM_TOOL_VARIANT=gold
export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
......@@ -14,7 +14,7 @@
//-----------------------------------------------------------------------------
module axi_streamio8_buffer
module axi_stream_io_8_buffer
(
input wire aclk,
input wire aresetn,
......
......@@ -15,7 +15,7 @@
//-----------------------------------------------------------------------------
module axi_streamio8_rxd_to_file
module axi_stream_io_8_rxd_to_file
#(parameter RXDFILENAME = "rxd.log",
parameter VERBOSE = 0)
(
......
......@@ -15,7 +15,7 @@
//-----------------------------------------------------------------------------
module axi_streamio8_txd_from_file
module axi_stream_io_8_txd_from_file
#(parameter TXDFILENAME = "txd.cmd",
parameter VERBOSE = 0)
(
......
......@@ -266,9 +266,9 @@ wire rxd8_ready;
wire rxd8_valid;
wire [7:0] rxd8_data ;
axi_streamio8_txd_from_file
axi_stream_io_8_txd_from_file
#(.TXDFILENAME(ADP_FILENAME))
u_axi_streamio8_txd_from_file
u_axi_stream_io_8_txd_from_file
(
.aclk (XTAL1),
.aresetn (NRST),
......@@ -278,8 +278,8 @@ axi_streamio8_txd_from_file
);
/*
axi_streamio8_buffer
u_axi_streamio8_buffer
axi_stream_io_8_buffer
u_axi_stream_io_8_buffer
(
.aclk (XTAL1),
.aresetn (NRST),
......@@ -316,9 +316,9 @@ ft1248x1_to_axi_streamio_v1_0
.txd_tdata8_o (rxd8_data)
);
axi_streamio8_rxd_to_file
axi_stream_io_8_rxd_to_file
#(.RXDFILENAME("ft1248_out.log"))
u_axi_streamio8_rxd_to_file
u_axi_stream_io_8_rxd_to_file
(
.aclk (XTAL1),
.aresetn (NRST),
......
//-----------------------------------------------------------------------------
// customised Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: $
//
// Revision : $Revision: $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Cortex-M0 example system
//-----------------------------------------------------------------------------
//
// ================= MCU System options ===============
// Option to select Cortex-M0+ processor in example system
+define+CORTEX_M0
// =================== Tarmac Logging =================
+define+USE_TARMAC
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ================= Top level file ===================
../verilog/tb_nanosoc.v
+incdir+../verilog
+incdir+/../verilog/soclabs_4x7_AhbMatrix
-y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
// ============= GLIB Generic Library path =============
../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
../../../../../GLIB/pads/verilog/PAD_VDDIO.v
../../../../../GLIB/pads/verilog/PAD_VSSIO.v
../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
../../../../../GLIB/pads/verilog/PAD_VSS.v
../../../../../GLIB/mem/verilog/SROM_Ax32.v
../../../../../GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
// ================= Testbench path ===================
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
// ============= MCU Module search path =============
-y ../verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
/// upgrade to AAA 'rel2' version
+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
../verilog/pl230_defs.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
../verilog/cmsdk_apb_usrt.v
// ============= Cortex-M0 Module search path =============
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
// ============= Cortex-M0 Include file search path =============
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
// =============Debug tester Include file search path =============
// ============= OVL support libraries =============
//+define+ASSERT_ON
//+define+OVL_ASSERT_ON
//+define+ARM_ASSERT_ON
//+define+ARM_AHB_ASSERT_ON
//+define+ARM_APB_ASSERT_ON
//+define+ARM_CMSDK_ASSERT_ON
// ============= Verification components =============
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/
///+incdir+/arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
///-y /arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl
//-----------------------------------------------------------------------------
// customised Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: $
//
// Revision : $Revision: $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Cortex-M0 example system
//-----------------------------------------------------------------------------
//
// ================= MCU System options ===============
// Option to select Cortex-M0+ processor in example system
+define+CORTEX_M0
// =================== Tarmac Logging =================
+define+USE_TARMAC
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ================= Top level file ===================
../verilog/tb_nanosoc.v
+incdir+../verilog
+incdir+/../verilog/soclabs_4x7_AhbMatrix
-y ../verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
// ================= Testbench path ===================
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
// ============= GLIB Generic Library path =============
../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
../../../../../GLIB/pads/verilog/PAD_VDDIO.v
../../../../../GLIB/pads/verilog/PAD_VSSIO.v
../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
../../../../../GLIB/pads/verilog/PAD_VSS.v
../../../../../GLIB/mem/verilog/SROM_Ax32.v
../../../../../GLIB/sync/verilog/SYNCHRONIZER_EDGES.v
// ============= IPLIB soclabs IP Library path =============
../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
../verilog/cmsdk_apb_usrt.v
// ============= MCU Module search path =============
-y ../verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog
//-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
/// upgrade to AAA 'rel2' version
+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
../verilog/pl230_defs.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
// ============= Cortex-M0 Module search path =============
// guts of core not exposed, periphery only
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
// ============= Cortex-M0 Include file search path =============
// guts of core not exposed, periphery only
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment