update IO library models

7e61ba67 · dwf1m12 · 88cac616 · 7e61ba67 · 7e61ba67 · 7e61ba67
Commit 7e61ba67 authored 2 years ago by dwf1m12
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
@@ -50,7 +50,11 @@
 +incdir+../verilog
 // =============   GLIB Generic Library path  =============
-../../../../../GLIB/pads/verilog/GLIB_PADLIB.v
+../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+../../../../../GLIB/pads/verilog/PAD_VDDIO.v
+../../../../../GLIB/pads/verilog/PAD_VSSIO.v
+../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
+../../../../../GLIB/pads/verilog/PAD_VSS.v
 ../../../../../GLIB/mem/verilog/SROM_Ax32.v
 // ================= Testbench path ===================

--- a/GLIB/pads/verilog/GLIB_PADLIB.v
+++ b/GLIB/pads/verilog/GLIB_PADLIB.v
 // GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_INOUT8MA_NOE (

--- a/GLIB/pads/verilog/PAD_ANALOG.v
+++ b/GLIB/pads/verilog/PAD_ANALOG.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 // VDDISOL

--- a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_INOUT8MA_NOE (

--- a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_INOUT8MA_OE (

--- a/GLIB/pads/verilog/PAD_VDDIO.v
+++ b/GLIB/pads/verilog/PAD_VDDIO.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_VDDIO (

--- a/GLIB/pads/verilog/PAD_VDDSOC.v
+++ b/GLIB/pads/verilog/PAD_VDDSOC.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 // core logic supply rails (1V0, 0V)

--- a/GLIB/pads/verilog/PAD_VSS.v
+++ b/GLIB/pads/verilog/PAD_VSS.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_VSS (

--- a/GLIB/pads/verilog/PAD_VSSIO.v
+++ b/GLIB/pads/verilog/PAD_VSSIO.v
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
+// soclabs generic IO pad model
-// only be used by a person authorised under and to the extent permitted
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-// by a subsisting licensing agreement from ARM Limited.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
+// Contributors
-//                ALL RIGHTS RESERVED
 //
-// This entire notice must be reproduced on all copies of this file
+// David Flynn (d.w.flynn@soton.ac.uk)
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
 //
-//      Revision            : $Revision: $
+// Copyright  2022, SoC Labs (www.soclabs.org)
-//
-//      Release Information : $ $
 //-----------------------------------------------------------------------------
 module PAD_VSSIO (