From 7e61ba6703d6928b7b5002837f79dd6b14d1f18e Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Wed, 13 Apr 2022 13:33:59 +0100 Subject: [PATCH] update IO library models --- .../cortex_m0_mcu/verilog/tbench_M0.vc | 6 +++++- GLIB/pads/verilog/GLIB_PADLIB.v | 17 +++++------------ GLIB/pads/verilog/PAD_ANALOG.v | 19 ++++++------------- GLIB/pads/verilog/PAD_INOUT8MA_NOE.v | 19 ++++++------------- GLIB/pads/verilog/PAD_INOUT8MA_OE.v | 19 ++++++------------- GLIB/pads/verilog/PAD_VDDIO.v | 19 ++++++------------- GLIB/pads/verilog/PAD_VDDSOC.v | 19 ++++++------------- GLIB/pads/verilog/PAD_VSS.v | 19 ++++++------------- GLIB/pads/verilog/PAD_VSSIO.v | 19 ++++++------------- 9 files changed, 52 insertions(+), 104 deletions(-) diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc index 13e0735..7faa42f 100644 --- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc +++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc @@ -50,7 +50,11 @@ +incdir+../verilog // ============= GLIB Generic Library path ============= -../../../../../GLIB/pads/verilog/GLIB_PADLIB.v +../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v +../../../../../GLIB/pads/verilog/PAD_VDDIO.v +../../../../../GLIB/pads/verilog/PAD_VSSIO.v +../../../../../GLIB/pads/verilog/PAD_VDDSOC.v +../../../../../GLIB/pads/verilog/PAD_VSS.v ../../../../../GLIB/mem/verilog/SROM_Ax32.v // ================= Testbench path =================== diff --git a/GLIB/pads/verilog/GLIB_PADLIB.v b/GLIB/pads/verilog/GLIB_PADLIB.v index 8ac1ac4..bc10d2b 100755 --- a/GLIB/pads/verilog/GLIB_PADLIB.v +++ b/GLIB/pads/verilog/GLIB_PADLIB.v @@ -1,20 +1,13 @@ // GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_INOUT8MA_NOE ( diff --git a/GLIB/pads/verilog/PAD_ANALOG.v b/GLIB/pads/verilog/PAD_ANALOG.v index 06207e9..2715fb3 100644 --- a/GLIB/pads/verilog/PAD_ANALOG.v +++ b/GLIB/pads/verilog/PAD_ANALOG.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- // VDDISOL diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v index f6220e5..42123e8 100644 --- a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v +++ b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_INOUT8MA_NOE ( diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v index d5d7944..12d3009 100644 --- a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v +++ b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_INOUT8MA_OE ( diff --git a/GLIB/pads/verilog/PAD_VDDIO.v b/GLIB/pads/verilog/PAD_VDDIO.v index 64581c0..7932481 100644 --- a/GLIB/pads/verilog/PAD_VDDIO.v +++ b/GLIB/pads/verilog/PAD_VDDIO.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_VDDIO ( diff --git a/GLIB/pads/verilog/PAD_VDDSOC.v b/GLIB/pads/verilog/PAD_VDDSOC.v index bb48fcd..2e97119 100644 --- a/GLIB/pads/verilog/PAD_VDDSOC.v +++ b/GLIB/pads/verilog/PAD_VDDSOC.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- // core logic supply rails (1V0, 0V) diff --git a/GLIB/pads/verilog/PAD_VSS.v b/GLIB/pads/verilog/PAD_VSS.v index ab407e1..07b87ce 100644 --- a/GLIB/pads/verilog/PAD_VSS.v +++ b/GLIB/pads/verilog/PAD_VSS.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_VSS ( diff --git a/GLIB/pads/verilog/PAD_VSSIO.v b/GLIB/pads/verilog/PAD_VSSIO.v index e27e9d8..d25ef36 100644 --- a/GLIB/pads/verilog/PAD_VSSIO.v +++ b/GLIB/pads/verilog/PAD_VSSIO.v @@ -1,20 +1,13 @@ -// GLIB_PADLIB.v +// from GLIB_PADLIB.v //----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. +// soclabs generic IO pad model +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // -// (C) COPYRIGHT 2009-2010 ARM Limited. -// ALL RIGHTS RESERVED +// Contributors // -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. +// David Flynn (d.w.flynn@soton.ac.uk) // -// Revision : $Revision: $ -// -// Release Information : $ $ +// Copyright © 2022, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- module PAD_VSSIO ( -- GitLab