diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
index 13e0735825a1ff2fb2b0621a461c10b66dcf8eb2..7faa42f374ba0c1b30c91d0b48c75f2482508097 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
@@ -50,7 +50,11 @@
 +incdir+../verilog
 
 // =============   GLIB Generic Library path  =============
-../../../../../GLIB/pads/verilog/GLIB_PADLIB.v
+../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+../../../../../GLIB/pads/verilog/PAD_VDDIO.v
+../../../../../GLIB/pads/verilog/PAD_VSSIO.v
+../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
+../../../../../GLIB/pads/verilog/PAD_VSS.v
 ../../../../../GLIB/mem/verilog/SROM_Ax32.v
 
 // ================= Testbench path ===================
diff --git a/GLIB/pads/verilog/GLIB_PADLIB.v b/GLIB/pads/verilog/GLIB_PADLIB.v
index 8ac1ac4b760a7af4a9954c058a782ed8834abb0f..bc10d2b212b1da281703606bffebda2e2b57e292 100755
--- a/GLIB/pads/verilog/GLIB_PADLIB.v
+++ b/GLIB/pads/verilog/GLIB_PADLIB.v
@@ -1,20 +1,13 @@
 // GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_INOUT8MA_NOE (
diff --git a/GLIB/pads/verilog/PAD_ANALOG.v b/GLIB/pads/verilog/PAD_ANALOG.v
index 06207e9f1a61a899277941b3187144813a6d14ab..2715fb3dbe5a03fcbdc5641d138495b7ce6bcdf3 100644
--- a/GLIB/pads/verilog/PAD_ANALOG.v
+++ b/GLIB/pads/verilog/PAD_ANALOG.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 // VDDISOL
diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
index f6220e56f7cf38b3c2efad989a6ee6506f7facea..42123e8d7ac8f9b825dadceaba8b8019ea0acf0e 100644
--- a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_INOUT8MA_NOE (
diff --git a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
index d5d794422e5787feec0fcb64c1c87654e167ff2c..12d3009903039b310860a697a0430744825d05a1 100644
--- a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_INOUT8MA_OE (
diff --git a/GLIB/pads/verilog/PAD_VDDIO.v b/GLIB/pads/verilog/PAD_VDDIO.v
index 64581c085f253b36f15d734cd1e8f4ba635b8e59..793248170190fc0cebee1b3355d19ef01230d7f5 100644
--- a/GLIB/pads/verilog/PAD_VDDIO.v
+++ b/GLIB/pads/verilog/PAD_VDDIO.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_VDDIO (
diff --git a/GLIB/pads/verilog/PAD_VDDSOC.v b/GLIB/pads/verilog/PAD_VDDSOC.v
index bb48fcd3519dd1d24fcc98556bf9d5c61ecd5b76..2e971192d8cf8834b02e23c2997db121e51324b0 100644
--- a/GLIB/pads/verilog/PAD_VDDSOC.v
+++ b/GLIB/pads/verilog/PAD_VDDSOC.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 // core logic supply rails (1V0, 0V)
diff --git a/GLIB/pads/verilog/PAD_VSS.v b/GLIB/pads/verilog/PAD_VSS.v
index ab407e13b77dc478c5bc29a8daffa2be4da7fbb9..07b87ce75b9a19404443d06a7c01bedeb4083c77 100644
--- a/GLIB/pads/verilog/PAD_VSS.v
+++ b/GLIB/pads/verilog/PAD_VSS.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_VSS (
diff --git a/GLIB/pads/verilog/PAD_VSSIO.v b/GLIB/pads/verilog/PAD_VSSIO.v
index e27e9d838bf8bdc3c46ef1dc72c1d39d794c9b00..d25ef361fb315640284a13be8ab1658e359e5b77 100644
--- a/GLIB/pads/verilog/PAD_VSSIO.v
+++ b/GLIB/pads/verilog/PAD_VSSIO.v
@@ -1,20 +1,13 @@
-// GLIB_PADLIB.v
+// from GLIB_PADLIB.v
 //-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
-//            (C) COPYRIGHT 2009-2010 ARM Limited.
-//                ALL RIGHTS RESERVED
+// Contributors
 //
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
+// David Flynn (d.w.flynn@soton.ac.uk)
 //
-//      Revision            : $Revision: $
-//
-//      Release Information : $ $
+// Copyright © 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 module PAD_VSSIO (