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Commit 7e61ba67 authored by dwf1m12's avatar dwf1m12
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update IO library models

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
+ 5
− 1
View file @ 7e61ba67
......@@ -50,7 +50,11 @@
+incdir+../verilog
// ============= GLIB Generic Library path =============
../../../../../GLIB/pads/verilog/GLIB_PADLIB.v
../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
../../../../../GLIB/pads/verilog/PAD_VDDIO.v
../../../../../GLIB/pads/verilog/PAD_VSSIO.v
../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
../../../../../GLIB/pads/verilog/PAD_VSS.v
../../../../../GLIB/mem/verilog/SROM_Ax32.v
// ================= Testbench path ===================
......
GLIB/pads/verilog/GLIB_PADLIB.v
+ 5
− 12
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// GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_INOUT8MA_NOE (
......
GLIB/pads/verilog/PAD_ANALOG.v
+ 6
− 13
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// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
// VDDISOL
......
GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_INOUT8MA_NOE (
......
GLIB/pads/verilog/PAD_INOUT8MA_OE.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_INOUT8MA_OE (
......
GLIB/pads/verilog/PAD_VDDIO.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_VDDIO (
......
GLIB/pads/verilog/PAD_VDDSOC.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
// core logic supply rails (1V0, 0V)
......
GLIB/pads/verilog/PAD_VSS.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_VSS (
......
GLIB/pads/verilog/PAD_VSSIO.v
+ 6
− 13
View file @ 7e61ba67
// GLIB_PADLIB.v
// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// (C) COPYRIGHT 2009-2010 ARM Limited.
// ALL RIGHTS RESERVED
// Contributors
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Revision : $Revision: $
//
// Release Information : $ $
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module PAD_VSSIO (
......
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