Verified Commit 41900e5b authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.{Data,Program}Memory: use dedicated port types

parent 001eaaaf
...@@ -5,21 +5,14 @@ package uk.ac.soton.ecs.can.core ...@@ -5,21 +5,14 @@ package uk.ac.soton.ecs.can.core
import chisel3._ import chisel3._
import chisel3.util.log2Ceil import chisel3.util.log2Ceil
import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.dataMemoryWords) private val addrWidth = log2Ceil(cfg.dataMemoryWords)
val read = IO(new Bundle { val read = IO(new MemoryReadIO(addrWidth, 512))
val en = Input(Bool()) val write = IO(new MemoryWriteIO(addrWidth, 512))
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(512.W))
})
val write = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(512.W))
})
private val mem = private val mem =
if (cfg.syncReadMemory) if (cfg.syncReadMemory)
......
...@@ -5,7 +5,7 @@ package uk.ac.soton.ecs.can.core ...@@ -5,7 +5,7 @@ package uk.ac.soton.ecs.can.core
import chisel3._ import chisel3._
import chisel3.util.log2Ceil import chisel3.util.log2Ceil
import uk.ac.soton.ecs.can.types.CanCoreControlWord import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
...@@ -19,16 +19,8 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { ...@@ -19,16 +19,8 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
}) })
val cw = IO(Output(UInt(cwWidth.W))) val cw = IO(Output(UInt(cwWidth.W)))
val read = IO(new Bundle { val read = IO(new MemoryReadIO(addrWidth, cwWidth))
val en = Input(Bool()) val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(cwWidth.W))
})
val write = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(cwWidth.W))
})
private val mem = private val mem =
if (cfg.syncReadMemory) if (cfg.syncReadMemory)
......
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class MemoryWriteIO(addrWidth: Int, dataWidth: Int) extends Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(dataWidth.W))
}
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