Tags

archive/snapshot/td-r2-investigation-2026-06-02

Archived branch snapshot/td-r2-investigation-2026-06-02 (consolidation 2026-06-10; see docs/AUTOCAL_CLOSURE_2026_06_10.md)

archive/worktree-agent-ad55ce030175b6a47

Archived branch worktree-agent-ad55ce030175b6a47 (consolidation 2026-06-10; see docs/AUTOCAL_CLOSURE_2026_06_10.md)

autocal-closure

Autocal closed for the v1 GPIO PHY — see docs/AUTOCAL_CLOSURE_2026_06_10.md

v33-ms-data-crossed

v33 milestone: first M->S application data crossing on silicon (2026-06-10).

Bitstream built from e2fefd4 + the deskew pipeline (c5f24b6) and run
with the M12 bootstrap (7702f07); this tag points at the first commit
whose tree matches what was on the boards.

Result: bilateral 16/16 cal+lock, FCSM=4 bilateral, 4-pkt AHB_TX burst
landed byte-perfect in the slave RX FIFO (hdr=0x00240000 p0=0xDA7A0000).
Master tap16 / slave tap7. Known residual: S->M credit decode
intermittent (~97%, marginal eye) — superseded by the new PHY.

baseline-pre-toolkit

v1.0-rc4-phc-deferred

v1.0-rc4: L1-L7 RTL stack, bilateral LINK_IDLE achieved on HW. PHC PHASE1 deferred to v2 pending credit-gate fix.

v1.0

TideLink v1.0 — unified trunk (USE_CLKBUF 16/16 FPGA + TSMC ASIC/GDSII + guards + RTL fixes + folded test/lint/CI coverage). Signoff-clean (WNS +0.409 / WHS +0.051); HW-validated 100% deterministic 16/16 on bridge1. Submodule axi-chiplet-controller @ 2f602d1. Supersedes the stale rc1-era v1.0@3ac342a.

v1.0-rc2

v1.0-rc1

v1-RC

TideLink v1-RC (2026-05-21)

Release-candidate tag for the v1 chiplet bring-up cycle. LOCAL-ONLY tag.

Contains:
- Bug #3 structural fix (autoneg mask phase) in sub a510bae
- HAL lint clean (0 errors in TideLink RTL scope)
- Verilator lint clean baseline
- 4 ASIC design docs (hard-IP, UPF, DFT, GPIO_PHY arch)
- SHORTCOMINGS + V2_DEFERRALS catalogue
- 4 CI integration plans (audit + FPGA + lint + cocotb)
- Lane-0+7 deep-dive + regression candidate hunt reports
- Reset-driven tb_early_exit_force_q (sim X-prop fix)
- Sticky SWI_LANE_STATUS instrumentation
- RDL preprocessor regex fix (recovers 11 dropped fields)
- ECC SECDED re-enable (4/4 cocotb regression PASS)
- Cocotb test consolidation (8 stale top-level copies dropped)

Known issue (deferred to v2): rebuild produces 12/16 deterministic
lane lock; morning's pre-built bitstream at mapstone-dev:/tmp/
tidelink_deploy/ continues to lock 14+/16 and is the v1 release
binary. See docs/V1_RC_PIVOT.md.

HW-validated on bridge1 (z2_02/z2_03 PYNQ-Z2 pair):
- Autoneg: master wins in 5ms, slave loses, both role_locked=1
- I2C bus: active, slave engaged (i2c_addr + sda_start seen)
- ECC: sim regression 4/4 pass

NEVER PUSH this tag to remote (standing constraint).

integ-step6

integ-step5

integ-step4

integ-step3

integ-step2

integ-step1-base