Tags

Tags give the ability to mark specific points in history as being important

  • v1.0

    c22416c1 · docs: RTL/FPGA/ASIC implementation status report · 
    TideLink v1.0 — unified trunk (USE_CLKBUF 16/16 FPGA + TSMC ASIC/GDSII + guards + RTL fixes + folded test/lint/CI coverage). Signoff-clean (WNS +0.409 / WHS +0.051); HW-validated 100% deterministic 16/16 on bridge1. Submodule axi-chiplet-controller @ 2f602d1. Supersedes the stale rc1-era v1.0@3ac342a.

  • v1-RC

    fcf6b3b5 · docs: v1-RC strategic pivot — use morning bitstream as release artifact · 
    TideLink v1-RC (2026-05-21)

Release-candidate tag for the v1 chiplet bring-up cycle. LOCAL-ONLY tag.

Contains:
- Bug #3 structural fix (autoneg mask phase) in sub a510bae
- HAL lint clean (0 errors in TideLink RTL scope)
- Verilator lint clean baseline
- 4 ASIC design docs (hard-IP, UPF, DFT, GPIO_PHY arch)
- SHORTCOMINGS + V2_DEFERRALS catalogue
- 4 CI integration plans (audit + FPGA + lint + cocotb)
- Lane-0+7 deep-dive + regression candidate hunt reports
- Reset-driven tb_early_exit_force_q (sim X-prop fix)
- Sticky SWI_LANE_STATUS instrumentation
- RDL preprocessor regex fix (recovers 11 dropped fields)
- ECC SECDED re-enable (4/4 cocotb regression PASS)
- Cocotb test consolidation (8 stale top-level copies dropped)

Known issue (deferred to v2): rebuild produces 12/16 deterministic
lane lock; morning's pre-built bitstream at mapstone-dev:/tmp/
tidelink_deploy/ continues to lock 14+/16 and is the v1 release
binary. See docs/V1_RC_PIVOT.md.

HW-validated on bridge1 (z2_02/z2_03 PYNQ-Z2 pair):
- Autoneg: master wins in 5ms, slave loses, both role_locked=1
- I2C bus: active, slave engaged (i2c_addr + sda_start seen)
- ECC: sim regression 4/4 pass

NEVER PUSH this tag to remote (standing constraint).