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SoCLabs
SoCDebug Tech
Commits
05574880d32139de3b4f3a8b5ff3b45f551751e5
Select Git revision
Branches
2
main
default
protected
feat_extio
2 results
socdebug_tech
socket
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Oct 08, 2024
support FPGA targets other than zynqplus
· 05574880
dwf1m12
authored
5 months ago
05574880
Oct 02, 2024
refactor socdebug for extio8x4 integration
· 05781fa3
dwf1m12
authored
5 months ago
05781fa3
Jul 04, 2023
Renamed f232h files
· 632ebe34
dam1n19
authored
1 year ago
632ebe34
Modified git submodules location
· 46ee6127
dam1n19
authored
1 year ago
46ee6127
Added flow for streamio
· 214ef8e9
dam1n19
authored
1 year ago
214ef8e9
Added makeflow for packaged ft1248 controller
· fcca357c
dam1n19
authored
1 year ago
fcca357c
Started Refactoring Ft1248 Socket
· 0824d133
dam1n19
authored
1 year ago
0824d133
Added UART Packaging
· 27140834
dam1n19
authored
1 year ago
27140834
Added UART AXI Master as sub repo
· 75e80cbe
dam1n19
authored
1 year ago
75e80cbe
Updated make recipies and removed unused ft1248 axi stream package
· 6afabad6
dam1n19
authored
1 year ago
6afabad6
Moved Vivado Socket into SoCDebug
· abe4e2cb
dam1n19
authored
1 year ago
abe4e2cb
Jun 22, 2023
Fixed io stream instantiation wiring and changed clock dividing to a parameter
· ec5a6083
dam1n19
authored
1 year ago
ec5a6083
Jun 02, 2023
Started Moving IP into Repo
· db6019d6
dam1n19
authored
1 year ago
db6019d6
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