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Created with Raphaël 2.2.020Jan5Nov8Oct429Aug29Jul8Jan10Jul6542130Jun2928232232block RX until RX-enable setmainmainupdate xilinx lifecycle to Production (was Pre-Production)support FPGA targets other than zynqplusupdate the FPGA IP components for extio controllerrefactor socdebug for extio8x4 integrationclean up the 'USRT' streamio modulefeat_extiofeat_extioadd TX/RX enable to usrt stream channels, and re-factor for EXTIO supportfix ADP Upload command count reportingfix floating RX stream ready outputFixed UART vendor variableRemoved MEM_INIT variable from lintAdded recursive projbranch filesupdate gitmodulesUpdated copy_to directory for fpga flowChanged package_socket dependenciesMerge branch 'socdebug-hal' into 'main'Renamed f232h filesModified git submodules locationAdded flow for streamioAdded makeflow for packaged ft1248 controllerStarted Refactoring Ft1248 SocketAdded UART PackagingAdded target for compiling UART to AXI Master componentAdded UART AXI Master as sub repoUpdated make recipies and removed unused ft1248 axi stream packageMoved Vivado Socket into SoCDebugft1248_control code clean up and hal waiversclean up adp_control with appropriate hal waiversUpdated TimescaleUpdated Lint FlowMoved Test IO filelist into this repoupdated lint flowadded header to filelistAdded Lint flow to SoCDebug - Needs to be linted!Renamed ADP_POLL to ADP_POLL0 to fix lint errirAdded SoCDebug Controller IP FilelistFixed io stream instantiation wiring and changed clock dividing to a parameterChanged default parameter values and fixed column alignmentRestructured Debug ControllerUpdate Name to SoCDebug