support FPGA targets other than zynqplus

socket/vivado_packages/extio8x4_axis_target_1.0/component.xml

@@ -240,7 +240,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9350a4b0</spirit:value>
+            <spirit:value>b0c1c61e</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -649,15 +649,29 @@
   <spirit:vendorExtensions>
     <xilinx:coreExtensions>
       <xilinx:supportedFamilies>
-        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplusHBM</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">aspartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
       </xilinx:supportedFamilies>
       <xilinx:taxonomies>
         <xilinx:taxonomy>/soclabsIP</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>extio8x4_axis_target_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
       <xilinx:definitionSource>package_project</xilinx:definitionSource>
-      <xilinx:coreRevision>2</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-10-01T17:09:36Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2024-10-08T16:30:59Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="ui.data.coregen.df@247831ce_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@3e3d1f50_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
@@ -672,12 +686,24 @@
         <xilinx:tag xilinx:name="ui.data.coregen.df@6bb013c9_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@4ec3d82_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@48dc1b5f_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@3f9bd21a_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@5b916f18_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@5e60f731_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@737a2f6c_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@2be947d1_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@3d3abef3_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@f992813_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@2bbbb719_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@531b8297_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@380be242_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@5a97ffa7_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@6c94eefd_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="574beea2"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bd4732b1"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="df8a00f1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="d4879326"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="06f7268c"/>
       <xilinx:targetDRCs>