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Commit 2e3ae3bc authored by dam1n19's avatar dam1n19
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Added additional Arm IP to Waiver

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lint/cortexm0_ip.bb
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...@@ -29,4 +29,17 @@ bb_list ...@@ -29,4 +29,17 @@ bb_list
// Exclude Cortex M0 Wake on Interrupt Controller as Arm IP // Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
designunit = cortexm0_wic; designunit = cortexm0_wic;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v; file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
// Exclude Cortex M0 Reset Send Set as Arm IP
designunit = cm0_rst_send_set;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v;
// Exclude Cortex M0 Reset Synchroniser as Arm IP
designunit = cm0_rst_sync;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v;
// Exclude Cortex M0 PMU as Arm IP
designunit = cortexm0_pmu;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v;
} }
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