diff --git a/lint/cortexm0_ip.bb b/lint/cortexm0_ip.bb
index aadce5560f5d10c417de035948f14b1adf2ad518..e0b08433f5efc7ab37b6bab084146943316c0c68 100644
--- a/lint/cortexm0_ip.bb
+++ b/lint/cortexm0_ip.bb
@@ -29,4 +29,17 @@ bb_list
     // Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
     designunit = cortexm0_wic;
     file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
+    
+    // Exclude Cortex M0 Reset Send Set as Arm IP
+    designunit = cm0_rst_send_set;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v;
+    
+    // Exclude Cortex M0 Reset Synchroniser as Arm IP
+    designunit = cm0_rst_sync;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v;
+    
+    // Exclude Cortex M0 PMU as Arm IP
+    designunit = cortexm0_pmu;
+    file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v;
+
 }
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