From 2e3ae3bc669358a1ee423bb8f2af6e8e5c628966 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 14:40:59 +0100
Subject: [PATCH] Added additional Arm IP to Waiver
---
lint/cortexm0_ip.bb | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/lint/cortexm0_ip.bb b/lint/cortexm0_ip.bb
index aadce55..e0b0843 100644
--- a/lint/cortexm0_ip.bb
+++ b/lint/cortexm0_ip.bb
@@ -29,4 +29,17 @@ bb_list
// Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
designunit = cortexm0_wic;
file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v;
+
+ // Exclude Cortex M0 Reset Send Set as Arm IP
+ designunit = cm0_rst_send_set;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v;
+
+ // Exclude Cortex M0 Reset Synchroniser as Arm IP
+ designunit = cm0_rst_sync;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v;
+
+ // Exclude Cortex M0 PMU as Arm IP
+ designunit = cortexm0_pmu;
+ file = $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v;
+
}
\ No newline at end of file
--
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