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.gitignore
View file @ 234233bf
...@@ -15,10 +15,16 @@ ASIC/*/Cadence/scripts/*.rpt ...@@ -15,10 +15,16 @@ ASIC/*/Cadence/scripts/*.rpt
ASIC/*/Cadence/scripts/*.tstamp ASIC/*/Cadence/scripts/*.tstamp
ASIC/*/Cadence/scripts/.cadence ASIC/*/Cadence/scripts/.cadence
ASIC/*/Cadence/scripts/.*
ASIC/*/Cadence/scripts/*.spec
ASIC/*/Cadence/scripts/*.sdf
ASIC/*/Cadence/scripts/*.gif
ASIC/*/Cadence/scripts/*.lef
ASIC/*/Cadence/scripts/result
ASIC/*/Cadence/scripts/nanosoc_chip_pads ASIC/*/Cadence/scripts/nanosoc_chip_pads
ASIC/*/Cadence/scripts/timingReports ASIC/*/Cadence/scripts/timingReports
ASIC/*/Cadence/scripts/*.db* ASIC/*/Cadence/scripts/*.db*
ASIC/*/Cadence/scripts/*.rpt ASIC/*/Cadence/scripts/*.rpt*
ASIC/*/Cadence/scripts/*.checkFPlan ASIC/*/Cadence/scripts/*.checkFPlan
ASIC/*/Cadence/scripts/*.ptiavg ASIC/*/Cadence/scripts/*.ptiavg
ASIC/*/Cadence/scripts/*.ptifiles ASIC/*/Cadence/scripts/*.ptifiles
......
ASIC/28pin/Cadence/scripts/genus.tcl
View file @ 234233bf
...@@ -10,6 +10,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_16K_LIB $RF_08K_ ...@@ -10,6 +10,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_16K_LIB $RF_08K_
read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
elaborate nanosoc_chip_pads elaborate nanosoc_chip_pads
apply_power_intent apply_power_intent
...@@ -61,6 +62,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_ ...@@ -61,6 +62,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.v write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.v
write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pins.vp write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pins.vp
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.sdf
#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains.rep #report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains.rep
#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup.rep #report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup.rep
#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers.rep #report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers.rep
......
ASIC/44pin/Cadence/scripts/genus.tcl
View file @ 234233bf
#-----------------------------------------------------------------------------
# NanoSoC gate synthesis script for Cadence Genus
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# run: genus -f genus.tcl
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# David Flynn (d.w.flynn@soton.ac.uk)
# Srimanth Tenneti
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/" set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
...@@ -6,19 +21,25 @@ set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib ...@@ -6,19 +21,25 @@ set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
create_library_domain domain1 create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER" set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER"
## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none
## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
elaborate nanosoc_chip_pads elaborate nanosoc_chip_pads
## -- Apply power intent and check library and CPF -- ##
apply_power_intent apply_power_intent
check_library > lib_check.log check_library > syn_lib_check.log
check_cpf > syn_cpf_check.log
check_cpf
commit_power_intent commit_power_intent
check_power_structure -license lpgxl check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
#set_db dft_scan_style muxed_scan #set_db dft_scan_style muxed_scan
...@@ -60,6 +81,9 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_ ...@@ -60,6 +81,9 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep #report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep #report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep #report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
......
ASIC/44pin/Cadence/scripts/io_plan.tcl
View file @ 234233bf
...@@ -22,8 +22,8 @@ delete_io_fillers -cell PFILLER0005 ...@@ -22,8 +22,8 @@ delete_io_fillers -cell PFILLER0005
read_io_file nanosoc_io_plan.io read_io_file nanosoc_io_plan.io
add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300 add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
add_io_fillers -cells PCORNER -prefix CORNER -side e -from 500 -to 3000 add_io_fillers -cells PCORNER -prefix CORNER -side e -from 1380 -to 3000
add_io_fillers -cells PCORNER -prefix CORNER -side s -from 500 -to 3000 add_io_fillers -cells PCORNER -prefix CORNER -side s -from 880 -to 2000
add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300 add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
add_io_fillers -cells PFILLER20 -prefix FILLER -side n add_io_fillers -cells PFILLER20 -prefix FILLER -side n
......
ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
View file @ 234233bf
...@@ -21,21 +21,18 @@ ...@@ -21,21 +21,18 @@
(inst name="uPAD_P1_01" offset=800.71 place_status=placed ) (inst name="uPAD_P1_01" offset=800.71 place_status=placed )
) )
(left (left
(inst name="uPAD_P0_04" offset=153.67 place_status=placed ) (inst name="uPAD_P0_04" offset=146.25 place_status=placed )
(inst name="uPAD_P0_05" offset=271.00 place_status=placed ) (inst name="uPAD_P0_05" offset=251.25 place_status=placed )
(inst name="RESERVED " offset=388.33 place_status=placed ) (inst name="uPAD_P0_03" offset=356.25 place_status=placed )
(inst name="RESERVED " offset=505.67 place_status=placed ) (inst name="uPAD_VDDACC_0" offset=461.25 place_status=placed )
(inst name="uPAD_P0_03" offset=149.29 place_status=placed ) (inst name="uPAD_VSS_0" offset=566.25 place_status=placed )
(inst name="uPAD_VDDACC_0" offset=257.86 place_status=placed ) (inst name="uPAD_CLK_I" offset=671.25 place_status=placed )
(inst name="uPAD_VSS_0" offset=366.43 place_status=placed ) (inst name="uPAD_VDD_0" offset=776.25 place_status=placed )
(inst name="uPAD_CLK_I" offset=475.00 place_status=placed ) (inst name="uPAD_VDDIO_0" offset=881.25 place_status=placed )
(inst name="uPAD_VDD_0" offset=583.57 place_status=placed ) (inst name="uPAD_SWDIO_IO" offset=986.25 place_status=placed )
(inst name="uPAD_VDDIO_0" offset=692.14 place_status=placed ) (inst name="uPAD_VSSIO_0" offset=1091.25 place_status=placed )
(inst name="uPAD_SWDIO_IO" offset=800.71 place_status=placed ) (inst name="uPAD_P0_06" offset=1196.25 place_status=placed )
(inst name="uPAD_VSSIO_0" offset=1444.33 place_status=placed ) (inst name="uPAD_P0_07" offset=1301.25 place_status=placed )
(inst name="RESERVED " offset=1561.67 place_status=placed )
(inst name="uPAD_P0_06" offset=1679.00 place_status=placed )
(inst name="uPAD_P0_07" offset=1796.33 place_status=placed )
) )
(bottom (bottom
(inst name="uPAD_P0_02" offset=149.29 place_status=placed ) (inst name="uPAD_P0_02" offset=149.29 place_status=placed )
...@@ -47,20 +44,17 @@ ...@@ -47,20 +44,17 @@
(inst name="uPAD_P0_00" offset=800.71 ) (inst name="uPAD_P0_00" offset=800.71 )
) )
(right (right
(inst name="uPAD_P1_07" offset=153.67 place_status=placed ) (inst name="uPAD_P1_07" offset=146.25 place_status=placed )
(inst name="uPAD_P1_06" offset=271.00 place_status=placed ) (inst name="uPAD_P1_06" offset=251.25 place_status=placed )
(inst name="RESERVED " offset=388.33 place_status=placed ) (inst name="uPAD_VSSIO_1" offset=356.25 place_status=placed )
(inst name="uPAD_VSSIO_1" offset=505.67 place_status=placed ) (inst name="uPAD_P1_03" offset=461.25 place_status=placed )
(inst name="uPAD_P1_03" offset=149.29 place_status=placed ) (inst name="uPAD_P1_02" offset=566.25 place_status=placed )
(inst name="uPAD_P1_02" offset=257.86 place_status=placed ) (inst name="uPAD_VDDACC_2" offset=671.25 place_status=placed )
(inst name="uPAD_VDDACC_2" offset=366.43 place_status=placed ) (inst name="uPAD_VDD_2" offset=776.25 place_status=placed )
(inst name="uPAD_VDD_2" offset=475.00 place_status=placed ) (inst name="uPAD_VSS_2" offset=881.25 place_status=placed )
(inst name="uPAD_VSS_2" offset=583.57 place_status=placed ) (inst name="uPAD_VDDIO_2" offset=986.25 place_status=placed )
(inst name="uPAD_VDDIO_2" offset=692.14 place_status=placed ) (inst name="uPAD_NRST_I" offset=1091.25 place_status=placed )
(inst name="uPAD_NRST_I" offset=800.71 place_status=placed ) (inst name="uPAD_P1_04" offset=1196.25 place_status=placed )
(inst name="RESERVED " offset=1444.33 place_status=placed ) (inst name="uPAD_P1_05" offset=1301.25 place_status=placed )
(inst name="RESERVED " offset=1561.67 place_status=placed )
(inst name="uPAD_P1_04" offset=1679.00 place_status=placed )
(inst name="uPAD_P1_05" offset=1796.33 place_status=placed )
) )
) )
ASIC/44pin/Cadence/scripts/place.tcl
View file @ 234233bf
...@@ -15,7 +15,7 @@ set_db place_global_uniform_density true ...@@ -15,7 +15,7 @@ set_db place_global_uniform_density true
### Placement Mode Config ### Placement Mode Config
set_db place_design_floorplan_mode false set_db place_design_floorplan_mode false
place_opt_design place_design
### Delay Calculation ### Delay Calculation
write_sdf design.sdf -ideal_clock_network write_sdf design.sdf -ideal_clock_network
ASIC/44pin/Cadence/scripts/place_macros.tcl
View file @ 234233bf
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#------------------------------------------------------------------------------------ #------------------------------------------------------------------------------------
# relative floorplan # relative floorplan
gui_set_draw_view fplan
delete_relative_floorplan -all delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
...@@ -18,7 +19,7 @@ create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_se ...@@ -18,7 +19,7 @@ create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_se
move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500} move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6} update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6}
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 5 add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1 create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
...@@ -26,3 +27,5 @@ create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_ ...@@ -26,3 +27,5 @@ create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
\ No newline at end of file
ASIC/60pin/Cadence/scripts/genus.tcl
View file @ 234233bf
...@@ -9,6 +9,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO ...@@ -9,6 +9,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO
read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
elaborate nanosoc_chip_pads elaborate nanosoc_chip_pads
apply_power_intent apply_power_intent
...@@ -60,6 +61,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_powe ...@@ -60,6 +61,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_powe
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vm write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vm
write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vp write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vp
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.sdf
report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_60pin.rep report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_60pin.rep
report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_60pin.rep report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_60pin.rep
report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_60pin.rep report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_60pin.rep
......
ASIC/accelerator_only/Cadence/scripts/genus.tcl 0 → 100644
View file @ 234233bf
set_db init_lib_search_path $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/
set BASE_LIB sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB"
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
elaborate accelerator_subsystem
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/accelerator_only/accel_constraints.sdc
set_db delete_unloaded_insts false
set_db optimize_constant_1_flops false
set_db optimize_constant_0_flops false
set_db syn_generic_effort high
set_db syn_map_effort high
syn_generic
syn_map
syn_opt
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_area_784.rep
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_timing_784.rep
report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_gates_784.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_power_784.rep
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/netlist/accel.v
ASIC/accelerator_only/accel_constraints.sdc 0 → 100644
View file @ 234233bf
#-----------------------------------------------------------------------------
# NanoSoC Constraints for Synthesis
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#### CLOCK DEFINITION
set EXTCLK "clk";
set_units -time ns;
set_units -capacitance pF;
set EXTCLK_PERIOD 4;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports HCLK]
set SKEW 0.200
set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
set MINRISE 0.20
set MAXRISE 0.25
set MINFALL 0.20
set MAXFALL 0.25
set_clock_transition -rise -min $MINRISE [get_clocks $EXTCLK]
set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
#### DELAY DEFINITION
set_max_capacitance 3 [all_outputs]
set_max_fanout 10 [all_inputs]
\ No newline at end of file
ASIC/constraints.sdc
View file @ 234233bf
...@@ -22,9 +22,9 @@ set SWDCLK_PERIOD 20; ...@@ -22,9 +22,9 @@ set SWDCLK_PERIOD 20;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK] create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK] create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.200 set SKEW 0.800
set_clock_uncertainty $SKEW [get_clocks $EXTCLK] set_clock_uncertainty [expr 0.15*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
set_clock_uncertainty $SKEW [get_clocks $SWDCLK] set_clock_uncertainty [expr 0.15*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
set MINRISE 0.20 set MINRISE 0.20
set MAXRISE 0.25 set MAXRISE 0.25
......
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
View file @ 234233bf
...@@ -74,15 +74,12 @@ module nanosoc_chip_pads ( ...@@ -74,15 +74,12 @@ module nanosoc_chip_pads (
wire swdclk_i; wire swdclk_i;
wire VSSIO; wire VSSIO;
assign VSSIO = VSS;
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Cortex-M0 nanosoc Microcontroller // Cortex-M0 nanosoc Microcontroller
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
nanosoc_chip u_nanosoc_chip ( nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS `ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD), .VDD (VDD),
.VSS (VSS), .VSS (VSS),
.VDDACC (VDDACC), .VDDACC (VDDACC),
......
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
View file @ 234233bf
...@@ -35,7 +35,6 @@ ...@@ -35,7 +35,6 @@
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller // Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// //
`define POWER_PINS
module nanosoc_chip_pads ( module nanosoc_chip_pads (
inout wire VDDIO, inout wire VDDIO,
inout wire VSSIO, inout wire VSSIO,
...@@ -55,64 +54,167 @@ module nanosoc_chip_pads ( ...@@ -55,64 +54,167 @@ module nanosoc_chip_pads (
//------------------------------------ //------------------------------------
// internal wires // internal wires
wire clk_i; localparam GPIO_TIO = 4;
wire test_i;
wire nrst_i;
wire [15:0] p0_i; // level-shifted input from pad wire pad_clk_i;
wire [15:0] p0_o; // output port drive wire pad_nrst_i;
wire [15:0] p0_e; // active high output drive enable (pad tech dependent) wire pad_test_i;
wire [15:0] p0_z; // active low output drive enable (pad tech dependent) wire pad_swdclk_i;
wire [15:0] p1_i; // level-shifted input from pad wire pad_swdio_i;
wire [15:0] p1_o; // output port drive wire pad_swdio_o;
wire [15:0] p1_e; // active high output drive enable (pad tech dependent) wire pad_swdio_e;
wire [15:0] p1_z; // active low output drive enable (pad tech dependent) wire pad_swdio_z;
wire [15:0] pad_gpio_port0_i ;
wire swdio_i; wire [15:0] pad_gpio_port0_o ;
wire swdio_o; wire [15:0] pad_gpio_port0_e ;
wire swdio_e; wire [15:0] pad_gpio_port0_z ;
wire swdio_z; wire [15:0] pad_gpio_port1_i ;
wire swdclk_i; wire [15:0] pad_gpio_port1_o ;
wire [15:0] pad_gpio_port1_e ;
// -------------------------------------------------------------------------------- wire [15:0] pad_gpio_port1_z ;
// Cortex-M0 nanosoc Microcontroller wire soc_nreset;
// -------------------------------------------------------------------------------- wire soc_diag_mode;
wire soc_diag_ctrl;
wire soc_scan_mode;
wire soc_scan_enable;
wire [GPIO_TIO-1:0] soc_scan_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_scan_out; //soc test status outputs
wire soc_bist_mode;
wire soc_bist_enable;
wire [GPIO_TIO-1:0] soc_bist_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_bist_out; //soc test status outputs
wire soc_alt_mode; // ALT MODE = UART
wire soc_uart_rxd_i; // UART RXD
wire soc_uart_txd_o = 1'b1; // UART TXD
wire soc_swd_mode; // SWD mode
wire soc_swd_clk_i; // SWDCLK
wire soc_swd_dio_i; // SWDIO tristate input
wire soc_swd_dio_o; // SWDIO trstate output
wire soc_swd_dio_e; // SWDIO tristate output enable
wire soc_swd_dio_z; // SWDIO tristate output hiz
wire [15:0] soc_gpio_port0_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port0_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port0_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port0_z; // GPIO SOC tristate output hiz
wire [15:0] soc_gpio_port1_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
assign pad_gpio_port0_e[15:GPIO_TIO] = soc_gpio_port0_e[15:GPIO_TIO];
assign pad_gpio_port0_z[15:GPIO_TIO] = soc_gpio_port0_z[15:GPIO_TIO];
assign soc_gpio_port1_i[15:GPIO_TIO] = pad_gpio_port1_i[15:GPIO_TIO];
assign pad_gpio_port1_o[15:GPIO_TIO] = soc_gpio_port1_o[15:GPIO_TIO];
assign pad_gpio_port1_e[15:GPIO_TIO] = soc_gpio_port1_e[15:GPIO_TIO];
assign pad_gpio_port1_z[15:GPIO_TIO] = soc_gpio_port1_z[15:GPIO_TIO];
wire tiehi = 1'b1;
wire tielo = 1'b0;
nanosoc_chip_cfg #(
.GPIO_TIO (GPIO_TIO)
)
u_nanosoc_chip_cfg
(
// Primary Inputs
.pad_clk_i (pad_clk_i )
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
,.pad_altin_i (pad_swdclk_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
,.pad_altio_z (pad_swdio_z ) // SWDIO/UARTTXD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-0 (user)
,.pad_gpio_port0_i (pad_gpio_port0_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port0_o (pad_gpio_port0_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port0_e (pad_gpio_port0_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port0_z (pad_gpio_port0_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-1 (system)
,.pad_gpio_port1_i (pad_gpio_port1_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port1_o (pad_gpio_port1_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port1_e (pad_gpio_port1_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port1_z (pad_gpio_port1_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
//SOC
,.soc_nreset (soc_nreset )
,.soc_diag_mode (soc_diag_mode )
,.soc_diag_ctrl (soc_diag_ctrl )
,.soc_scan_mode (soc_scan_mode )
,.soc_scan_enable (soc_scan_enable )
,.soc_scan_in (soc_scan_in ) // soc test scan chain inputs
,.soc_scan_out (soc_scan_out ) // soc test scan chain outputs
,.soc_bist_mode (soc_bist_mode )
,.soc_bist_enable (soc_bist_enable )
,.soc_bist_in (soc_bist_in ) // soc bist control inputs
,.soc_bist_out (soc_bist_out ) // soc test status outputs
,.soc_alt_mode (soc_alt_mode )// ALT MODE = UART
,.soc_uart_rxd_i (soc_uart_rxd_i ) // UART RXD
,.soc_uart_txd_o (soc_uart_txd_o ) // UART TXD
,.soc_swd_mode (soc_swd_mode ) // SWD mode
,.soc_swd_clk_i (soc_swd_clk_i ) // SWDCLK
,.soc_swd_dio_i (soc_swd_dio_i ) // SWDIO tristate input
,.soc_swd_dio_o (soc_swd_dio_o ) // SWDIO trstate output
,.soc_swd_dio_e (soc_swd_dio_e ) // SWDIO tristate output enable
,.soc_swd_dio_z (soc_swd_dio_z ) // SWDIO tristate output hiz
,.soc_gpio_port0_i (soc_gpio_port0_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port0_o (soc_gpio_port0_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port0_e (soc_gpio_port0_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port0_z (soc_gpio_port0_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
,.soc_gpio_port1_i (soc_gpio_port1_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port1_o (soc_gpio_port1_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port1_e (soc_gpio_port1_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port1_z (soc_gpio_port1_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
);
nanosoc_chip u_nanosoc_chip ( nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS `ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD), .VDD (VDD),
.VSS (VSS), .VSS (VSS),
.VDDACC (VDDACC), .VDDACC (VDDACC),
`endif `endif
.clk_i(clk_i), `ifdef ASIC_TEST_PORTS
.test_i(test_i), .diag_mode (soc_diag_mode ),
.nrst_i(nrst_i), .diag_ctrl (soc_diag_ctrl ),
.p0_i(p0_i), // level-shifted input from pad .scan_mode (soc_scan_mode ),
.p0_o(p0_o), // output port drive .scan_enable (soc_scan_enable ),
.p0_e(p0_e), // active high output drive enable (pad tech dependent) .scan_in (soc_scan_in ), // soc test scan chain inputs
.p0_z(p0_z), // active low output drive enable (pad tech dependent) .scan_out (soc_scan_out ), // soc test scan chain outputs
.p1_i(p1_i), // level-shifted input from pad .bist_mode (soc_bist_mode ),
.p1_o(p1_o), // output port drive .bist_enable (soc_bist_enable ),
.p1_e(p1_e), // active high output drive enable (pad tech dependent) .bist_in (soc_bist_in ), // soc bist control inputs
.p1_z(p1_z), // active low output drive enable (pad tech dependent) .bist_out (soc_bist_out ), // soc test status outputs
.swdio_i(swdio_i), .alt_mode (soc_alt_mode )// ALT MODE = UART
.swdio_o(swdio_o), .uart_rxd_i (soc_uart_rxd_i ) // UART RXD
.swdio_e(swdio_e), .uart_txd_o (soc_uart_txd_o ) // UART TXD
.swdio_z(swdio_z), .swd_mode (soc_swd_mode ), // SWD mode
.swdclk_i(swdclk_i) `endif
.clk_i(pad_clk_i),
.test_i(soc_scan_mode),
.nrst_i(soc_nreset),
.p0_i(soc_gpio_port0_i), // level-shifted input from pad
.p0_o(soc_gpio_port0_o), // output port drive
.p0_e(soc_gpio_port0_e), // active high output drive enable (pad tech dependent)
.p0_z(soc_gpio_port0_z), // active low output drive enable (pad tech dependent)
.p1_i(soc_gpio_port1_i), // level-shifted input from pad
.p1_o(soc_gpio_port1_o), // output port drive
.p1_e(soc_gpio_port1_e), // active high output drive enable (pad tech dependent)
.p1_z(soc_gpio_port1_z), // active low output drive enable (pad tech dependent)
.swdio_i(soc_swd_dio_i),
.swdio_o(soc_swd_dio_o),
.swdio_e(soc_swd_dio_e),
.swdio_z(soc_swd_dio_z),
.swdclk_i(soc_swd_clk_i)
); );
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
wire dft_sdi_1, dft_sdi_2, dft_sdo_1, dft_sdo_2;
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping) // IO pad (TSMC 65nm specific Library napping)
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Pad IO power supplies // Pad IO power supplies
...@@ -179,7 +281,7 @@ PVDD1CDG uPAD_VDDACC_2( ...@@ -179,7 +281,7 @@ PVDD1CDG uPAD_VDDACC_2(
PRDW0408SCDG uPAD_CLK_I ( PRDW0408SCDG uPAD_CLK_I (
.IE(tiehi), .IE(tiehi),
.C(clk_i), .C(pad_clk_i),
.PE(tielo), .PE(tielo),
.DS(tielo), .DS(tielo),
.I(tielo), .I(tielo),
...@@ -189,7 +291,7 @@ PRDW0408SCDG uPAD_CLK_I ( ...@@ -189,7 +291,7 @@ PRDW0408SCDG uPAD_CLK_I (
PRDW0408SCDG uPAD_TEST_I ( PRDW0408SCDG uPAD_TEST_I (
.IE(tiehi), .IE(tiehi),
.C(test_i), .C(pad_test_i),
.PE(tielo), .PE(tielo),
.DS(tielo), .DS(tielo),
.I(tielo), .I(tielo),
...@@ -199,7 +301,7 @@ PRDW0408SCDG uPAD_TEST_I ( ...@@ -199,7 +301,7 @@ PRDW0408SCDG uPAD_TEST_I (
PRDW0408SCDG uPAD_NRST_I ( PRDW0408SCDG uPAD_NRST_I (
.IE(tiehi), .IE(tiehi),
.C(nrst_i), .C(pad_nrst_i),
.PE(tielo), .PE(tielo),
.DS(tielo), .DS(tielo),
.I(tielo), .I(tielo),
...@@ -208,18 +310,18 @@ PRDW0408SCDG uPAD_NRST_I ( ...@@ -208,18 +310,18 @@ PRDW0408SCDG uPAD_NRST_I (
); );
PRDW0408SCDG uPAD_SWDIO_IO ( PRDW0408SCDG uPAD_SWDIO_IO (
.IE(swdio_z), .IE(pad_swdio_z),
.C(swdio_i), .C(pad_swdio_i),
.PE(tielo), .PE(tielo),
.DS(tielo), .DS(tielo),
.I(swdio_o), .I(pad_swdio_o),
.OEN(swdio_z), .OEN(pad_swdio_z),
.PAD(SWDIO) .PAD(SWDIO)
); );
PRDW0408SCDG uPAD_SWDCK_I ( PRDW0408SCDG uPAD_SWDCK_I (
.IE(tiehi), .IE(tiehi),
.C(swdclk_i), .C(pad_swdclk_i),
.PE(tielo), .PE(tielo),
.DS(tielo), .DS(tielo),
.I(tielo), .I(tielo),
...@@ -230,184 +332,184 @@ PRDW0408SCDG uPAD_SWDCK_I ( ...@@ -230,184 +332,184 @@ PRDW0408SCDG uPAD_SWDCK_I (
// GPI.I Port 0 x 16 // GPI.I Port 0 x 16
PRDW0408SCDG uPAD_P0_00 ( PRDW0408SCDG uPAD_P0_00 (
.IE(p0_z[00]), .IE(pad_gpio_port0_z[00]),
.C(p0_i[00]), .C(pad_gpio_port0_i[00]),
.PE(p0_z[00]&p0_o[00]), .PE(pad_gpio_port0_z[00]&pad_gpio_port0_o[00]),
.DS(tielo), .DS(tielo),
.I(p0_o[00]), .I(pad_gpio_port0_o[00]),
.OEN(p0_z[00]), .OEN(pad_gpio_port0_z[00]),
.PAD(P0[00]) .PAD(P0[00])
); );
PRDW0408SCDG uPAD_P0_01 ( PRDW0408SCDG uPAD_P0_01 (
.IE(p0_z[01]), .IE(pad_gpio_port0_z[01]),
.C(p0_i[01]), .C(pad_gpio_port0_i[01]),
.PE(p0_z[01]&p0_o[01]), .PE(pad_gpio_port0_z[01]&pad_gpio_port0_o[01]),
.DS(tielo), .DS(tielo),
.I(p0_o[01]), .I(pad_gpio_port0_o[01]),
.OEN(p0_z[01]), .OEN(pad_gpio_port0_z[01]),
.PAD(P0[01]) .PAD(P0[01])
); );
PRDW0408SCDG uPAD_P0_02 ( PRDW0408SCDG uPAD_P0_02 (
.IE(p0_z[02]), .IE(pad_gpio_port0_z[02]),
.C(p0_i[02]), .C(pad_gpio_port0_i[02]),
.PE(p0_z[02]&p0_o[02]), .PE(pad_gpio_port0_z[02]&pad_gpio_port0_o[02]),
.DS(tielo), .DS(tielo),
.I(p0_o[02]), .I(pad_gpio_port0_o[02]),
.OEN(p0_z[02]), .OEN(pad_gpio_port0_z[02]),
.PAD(P0[02]) .PAD(P0[02])
); );
PRDW0408SCDG uPAD_P0_03 ( PRDW0408SCDG uPAD_P0_03 (
.IE(p0_z[03]), .IE(pad_gpio_port0_z[03]),
.C(p0_i[03]), .C(pad_gpio_port0_i[03]),
.PE(p0_z[03]&p0_o[03]), .PE(pad_gpio_port0_z[03]&pad_gpio_port0_o[03]),
.DS(tielo), .DS(tielo),
.I(p0_o[03]), .I(pad_gpio_port0_o[03]),
.OEN(p0_z[03]), .OEN(pad_gpio_port0_z[03]),
.PAD(P0[03]) .PAD(P0[03])
); );
PRDW0408SCDG uPAD_P0_04 ( PRDW0408SCDG uPAD_P0_04 (
.IE(p0_z[04]), .IE(pad_gpio_port0_z[04]),
.C(p0_i[04]), .C(pad_gpio_port0_i[04]),
.PE(p0_z[04]&p0_o[04]), .PE(pad_gpio_port0_z[04]&pad_gpio_port0_o[04]),
.DS(tielo), .DS(tielo),
.I(p0_o[04]), .I(pad_gpio_port0_o[04]),
.OEN(p0_z[04]), .OEN(pad_gpio_port0_z[04]),
.PAD(P0[04]) .PAD(P0[04])
); );
PRDW0408SCDG uPAD_P0_05 ( PRDW0408SCDG uPAD_P0_05 (
.IE(p0_z[05]), .IE(pad_gpio_port0_z[05]),
.C(p0_i[05]), .C(pad_gpio_port0_i[05]),
.PE(p0_z[05]&p0_o[05]), .PE(pad_gpio_port0_z[05]&pad_gpio_port0_o[05]),
.DS(tielo), .DS(tielo),
.I(p0_o[05]), .I(pad_gpio_port0_o[05]),
.OEN(p0_z[05]), .OEN(pad_gpio_port0_z[05]),
.PAD(P0[05]) .PAD(P0[05])
); );
PRDW0408SCDG uPAD_P0_06 ( PRDW0408SCDG uPAD_P0_06 (
.IE(p0_z[06]), .IE(pad_gpio_port0_z[06]),
.C(p0_i[06]), .C(pad_gpio_port0_i[06]),
.PE(p0_z[06]&p0_o[06]), .PE(pad_gpio_port0_z[06]&pad_gpio_port0_o[06]),
.DS(tielo), .DS(tielo),
.I(p0_o[06]), .I(pad_gpio_port0_o[06]),
.OEN(p0_z[06]), .OEN(pad_gpio_port0_z[06]),
.PAD(P0[06]) .PAD(P0[06])
); );
PRDW0408SCDG uPAD_P0_07 ( PRDW0408SCDG uPAD_P0_07 (
.IE(p0_z[07]), .IE(pad_gpio_port0_z[07]),
.C(p0_i[07]), .C(pad_gpio_port0_i[07]),
.PE(p0_z[07]&p0_o[07]), .PE(pad_gpio_port0_z[07]&pad_gpio_port0_o[07]),
.DS(tielo), .DS(tielo),
.I(p0_o[07]), .I(pad_gpio_port0_o[07]),
.OEN(p0_z[07]), .OEN(pad_gpio_port0_z[07]),
.PAD(P0[07]) .PAD(P0[07])
); );
// GPI.I Port 1 x 16 // GPI.I Port 1 x 16
PRDW0408SCDG uPAD_P1_00 ( PRDW0408SCDG uPAD_P1_00 (
.IE(p1_z[00]), .IE(pad_gpio_port1_z[00]),
.C(p1_i[00]), .C(pad_gpio_port1_i[00]),
.PE(p1_z[00]&p1_o[00]), .PE(pad_gpio_port1_z[00]&pad_gpio_port1_o[00]),
.DS(tielo), .DS(tielo),
.I(p1_o[00]), .I(pad_gpio_port1_o[00]),
.OEN(p1_z[00]), .OEN(pad_gpio_port1_z[00]),
.PAD(P1[00]) .PAD(P1[00])
); );
PRDW0408SCDG uPAD_P1_01 ( PRDW0408SCDG uPAD_P1_01 (
.IE(p1_z[01]), .IE(pad_gpio_port1_z[01]),
.C(p1_i[01]), .C(pad_gpio_port1_i[01]),
.PE(p1_z[01]&p1_o[01]), .PE(pad_gpio_port1_z[01]&pad_gpio_port1_o[01]),
.DS(tielo), .DS(tielo),
.I(p1_o[01]), .I(pad_gpio_port1_o[01]),
.OEN(p1_z[01]), .OEN(pad_gpio_port1_z[01]),
.PAD(P1[01]) .PAD(P1[01])
); );
PRDW0408SCDG uPAD_P1_02 ( PRDW0408SCDG uPAD_P1_02 (
.IE(p1_z[02]), .IE(pad_gpio_port1_z[02]),
.C(p1_i[02]), .C(pad_gpio_port1_i[02]),
.PE(p1_z[02]&p1_o[02]), .PE(pad_gpio_port1_z[02]&pad_gpio_port1_o[02]),
.DS(tielo), .DS(tielo),
.I(p1_o[02]), .I(pad_gpio_port1_o[02]),
.OEN(p1_z[02]), .OEN(pad_gpio_port1_z[02]),
.PAD(P1[02]) .PAD(P1[02])
); );
PRDW0408SCDG uPAD_P1_03 ( PRDW0408SCDG uPAD_P1_03 (
.IE(p1_z[03]), .IE(pad_gpio_port1_z[03]),
.C(p1_i[03]), .C(pad_gpio_port1_i[03]),
.PE(p1_z[03]&p1_o[03]), .PE(pad_gpio_port1_z[03]&pad_gpio_port1_o[03]),
.DS(tielo), .DS(tielo),
.I(p1_o[03]), .I(pad_gpio_port1_o[03]),
.OEN(p1_z[03]), .OEN(pad_gpio_port1_z[03]),
.PAD(P1[03]) .PAD(P1[03])
); );
PRDW0408SCDG uPAD_P1_04 ( PRDW0408SCDG uPAD_P1_04 (
.IE(p1_z[04]), .IE(pad_gpio_port1_z[04]),
.C(p1_i[04]), .C(pad_gpio_port1_i[04]),
.PE(p1_z[04]&p1_o[04]), .PE(pad_gpio_port1_z[04]&pad_gpio_port1_o[04]),
.DS(tielo), .DS(tielo),
.I(p1_o[04]), .I(pad_gpio_port1_o[04]),
.OEN(p1_z[04]), .OEN(pad_gpio_port1_z[04]),
.PAD(P1[04]) .PAD(P1[04])
); );
PRDW0408SCDG uPAD_P1_05 ( PRDW0408SCDG uPAD_P1_05 (
.IE(p1_z[05]), .IE(pad_gpio_port1_z[05]),
.C(p1_i[05]), .C(pad_gpio_port1_i[05]),
.PE(p1_z[05]&p1_o[05]), .PE(pad_gpio_port1_z[05]&pad_gpio_port1_o[05]),
.DS(tielo), .DS(tielo),
.I(p1_o[05]), .I(pad_gpio_port1_o[05]),
.OEN(p1_z[05]), .OEN(pad_gpio_port1_z[05]),
.PAD(P1[05]) .PAD(P1[05])
); );
PRDW0408SCDG uPAD_P1_06 ( PRDW0408SCDG uPAD_P1_06 (
.IE(p1_z[06]), .IE(pad_gpio_port1_z[06]),
.C(p1_i[06]), .C(pad_gpio_port1_i[06]),
.PE(p1_z[06]&p1_o[06]), .PE(pad_gpio_port1_z[06]&pad_gpio_port1_o[06]),
.DS(tielo), .DS(tielo),
.I(p1_o[06]), .I(pad_gpio_port1_o[06]),
.OEN(p1_z[06]), .OEN(pad_gpio_port1_z[06]),
.PAD(P1[06]) .PAD(P1[06])
); );
PRDW0408SCDG uPAD_P1_07 ( PRDW0408SCDG uPAD_P1_07 (
.IE(p1_z[07]), .IE(pad_gpio_port1_z[07]),
.C(p1_i[07]), .C(pad_gpio_port1_i[07]),
.PE(p1_z[07]&p1_o[07]), .PE(pad_gpio_port1_z[07]&pad_gpio_port1_o[07]),
.DS(tielo), .DS(tielo),
.I(p1_o[07]), .I(pad_gpio_port1_o[07]),
.OEN(p1_z[07]), .OEN(pad_gpio_port1_z[07]),
.PAD(P1[07]) .PAD(P1[07])
); );
assign p0_i[8] = p0_o[8] & p0_e[8]; assign pad_gpio_port0_i[8] = pad_gpio_port0_o[8] & pad_gpio_port0_e[8];
assign p0_i[9] = p0_o[9] & p0_e[9]; assign pad_gpio_port0_i[9] = pad_gpio_port0_o[9] & pad_gpio_port0_e[9];
assign p0_i[10] = p0_o[10] & p0_e[10]; assign pad_gpio_port0_i[10] = pad_gpio_port0_o[10] & pad_gpio_port0_e[10];
assign p0_i[11] = p0_o[11] & p0_e[11]; assign pad_gpio_port0_i[11] = pad_gpio_port0_o[11] & pad_gpio_port0_e[11];
assign p0_i[12] = p0_o[12] & p0_e[12]; assign pad_gpio_port0_i[12] = pad_gpio_port0_o[12] & pad_gpio_port0_e[12];
assign p0_i[13] = p0_o[13] & p0_e[13]; assign pad_gpio_port0_i[13] = pad_gpio_port0_o[13] & pad_gpio_port0_e[13];
assign p0_i[14] = p0_o[14] & p0_e[14]; assign pad_gpio_port0_i[14] = pad_gpio_port0_o[14] & pad_gpio_port0_e[14];
assign p0_i[15] = p0_o[15] & p0_e[15]; assign pad_gpio_port0_i[15] = pad_gpio_port0_o[15] & pad_gpio_port0_e[15];
assign p1_i[8] = p1_o[8] & p1_e[8]; assign pad_gpio_port1_i[8] = pad_gpio_port1_o[8] & pad_gpio_port1_e[8];
assign p1_i[9] = p1_o[9] & p1_e[9]; assign pad_gpio_port1_i[9] = pad_gpio_port1_o[9] & pad_gpio_port1_e[9];
assign p1_i[10] = p1_o[10] & p1_e[10]; assign pad_gpio_port1_i[10] = pad_gpio_port1_o[10] & pad_gpio_port1_e[10];
assign p1_i[11] = p1_o[11] & p1_e[11]; assign pad_gpio_port1_i[11] = pad_gpio_port1_o[11] & pad_gpio_port1_e[11];
assign p1_i[12] = p1_o[12] & p1_e[12]; assign pad_gpio_port1_i[12] = pad_gpio_port1_o[12] & pad_gpio_port1_e[12];
assign p1_i[13] = p1_o[13] & p1_e[13]; assign pad_gpio_port1_i[13] = pad_gpio_port1_o[13] & pad_gpio_port1_e[13];
assign p1_i[14] = p1_o[14] & p1_e[14]; assign pad_gpio_port1_i[14] = pad_gpio_port1_o[14] & pad_gpio_port1_e[14];
assign p1_i[15] = p1_o[15] & p1_e[15]; assign pad_gpio_port1_i[15] = pad_gpio_port1_o[15] & pad_gpio_port1_e[15];
endmodule endmodule
......
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
View file @ 234233bf
...@@ -80,8 +80,6 @@ module nanosoc_chip_pads ( ...@@ -80,8 +80,6 @@ module nanosoc_chip_pads (
nanosoc_chip u_nanosoc_chip ( nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS `ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD), .VDD (VDD),
.VSS (VSS), .VSS (VSS),
.VDDACC (VDDACC), .VDDACC (VDDACC),
......
flist/nanosoc_ASIC.flist
View file @ 234233bf
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
// NanoSoC Chip Pads Level // NanoSoC Chip Pads Level
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
$(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_40pin.v // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
// Include NanoSoC IP // Include NanoSoC IP
......
software/common/debug_tests/debug_tests.h
View file @ 234233bf
...@@ -39,29 +39,19 @@ ...@@ -39,29 +39,19 @@
// //
// CM0_MCU GPIO0 -------------------------------------- Debug Tester // CM0_MCU GPIO0 -------------------------------------- Debug Tester
// //
// GPIO[15] 7 <----------------------------------------< Running // GPIO[7] 7 <----------------------------------------< Running
// GPIO[14] 6 <----------------------------------------< Error // GPIO[6] 6 <----------------------------------------< Error
// GPIO[13] 5 >----------------------------------------> Function Strobe // GPIO[5] 5 >----------------------------------------> Function Strobe
// GPIO[12] 4 >----------------------------------------> Function Select bit 4 // GPIO[4] 4 >----------------------------------------> Function Select bit 4
// GPIO[11] 3 >----------------------------------------> Function Select bit 3 // GPIO[3] 3 >----------------------------------------> Function Select bit 3
// GPIO[10] 2 >----------------------------------------> Function Select bit 2 // GPIO[2] 2 >----------------------------------------> Function Select bit 2
// GPIO[9] 1 >----------------------------------------> Function Select bit 1 // GPIO[1] 1 >----------------------------------------> Function Select bit 1
// GPIO[8] 0 >----------------------------------------> Function Select bit 0 // GPIO[0] 0 >----------------------------------------> Function Select bit 0
// #define DEBUG_BIT_LOC 0 //GPIO[0] is the ls bit of Function Select
#define DEBUG_BIT_LOC 8 //GPIO[8] is the least bit of Function Select #define DEBUG_CMD 0x3f //GPIO [5:0]
#define DEBUG_CMD 0x3f<<8 //GPIO [13:8] #define DEBUG_STROBE 0x20 //GPIO [5]
#define DEBUG_STROBE 0x00002000 //GPIO [13] #define DEBUG_ERROR 0x40 //GPIO [6]
#define DEBUG_ERROR 0x00004000 //GPIO [14] #define DEBUG_RUNNING 0x80 //GPIO [7]
#define DEBUG_RUNNING 0x00008000 //GPIO [15]
// GPIO1[7] 7
// GPIO1[6] 6
// GPIO1[5] 5
// GPIO1[4] 4
// GPIO1[3] 3
// GPIO1[2] 2
// GPIO1[1] 1
// GPIO1[0] 0
// CM0 MCU's view of the memory shared with the debugtester // CM0 MCU's view of the memory shared with the debugtester
......
testcodes/generic/mcu_debugtester_interface.h
View file @ 234233bf
...@@ -69,30 +69,19 @@ extern uint32_t CheckDebugTester(void); ...@@ -69,30 +69,19 @@ extern uint32_t CheckDebugTester(void);
// //
// CM0_MCU GPIO0 -------------------------------------- Debug Tester // CM0_MCU GPIO0 -------------------------------------- Debug Tester
// //
// GPIO[15] 7 <----------------------------------------< Running // GPIO[7] 7 <----------------------------------------< Running
// GPIO[14] 6 <----------------------------------------< Error // GPIO[6] 6 <----------------------------------------< Error
// GPIO[13] 5 >----------------------------------------> Function Strobe // GPIO[5] 5 >----------------------------------------> Function Strobe
// GPIO[12] 4 >----------------------------------------> Function Select bit 4 // GPIO[4] 4 >----------------------------------------> Function Select bit 4
// GPIO[11] 3 >----------------------------------------> Function Select bit 3 // GPIO[3] 3 >----------------------------------------> Function Select bit 3
// GPIO[10] 2 >----------------------------------------> Function Select bit 2 // GPIO[2] 2 >----------------------------------------> Function Select bit 2
// GPIO[9] 1 >----------------------------------------> Function Select bit 1 // GPIO[1] 1 >----------------------------------------> Function Select bit 1
// GPIO[8] 0 >----------------------------------------> Function Select bit 0 // GPIO[0] 0 >----------------------------------------> Function Select bit 0
// #define DEBUG_BIT_LOC 0 //GPIO[0] is the ls bit of Function Select
#define DEBUG_BIT_LOC 8 //GPIO[8] is the least bit of Function Select #define DEBUG_CMD 0x3f //GPIO [5:0]
#define DEBUG_CMD 0x3f<<8 //GPIO [13:8] #define DEBUG_STROBE 0x20 //GPIO [5]
#define DEBUG_STROBE 0x00002000 //GPIO [13] #define DEBUG_ERROR 0x40 //GPIO [6]
#define DEBUG_ERROR 0x00004000 //GPIO [14] #define DEBUG_RUNNING 0x80 //GPIO [7]
#define DEBUG_RUNNING 0x00008000 //GPIO [15]
// GPIO1[7] 7
// GPIO1[6] 6
// GPIO1[5] 5
// GPIO1[4] 4
// GPIO1[3] 3
// GPIO1[2] 2
// GPIO1[1] 1
// GPIO1[0] 0
// CMSDK example MCU's view of the memory shared with the debugtester // CMSDK example MCU's view of the memory shared with the debugtester
// (4 words above stack top) // (4 words above stack top)
......
verif/tb/verilog/nanosoc_tb.v
View file @ 234233bf
...@@ -103,11 +103,29 @@ SROM_Ax32 ...@@ -103,11 +103,29 @@ SROM_Ax32
.SEL(1'b0), .SEL(1'b0),
.RDATA( ) .RDATA( )
); );
`ifdef SDF_SIM
initial
$sdf_annotate ( "../../../src/rtl/nanosoc_chip_pads_44pin.sdf"
, u_nanosoc_chip_pads
,
, "sdf_annotate.log"
, "MAXIMUM"
);
`endif // SDF_SIM
`ifdef VCD_SIM
initial begin
$dumpfile("waves.vcd");
$dumpvars(6,u_nanosoc_chip_pads);
end
`endif // VCD_SIM
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller // Cortex-M0/Cortex-M0+ Microcontroller
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
`ifdef SDF_SIM
nanosoc_chip_pads nanosoc_chip_pads
u_nanosoc_chip_pads ( u_nanosoc_chip_pads (
`ifdef POWER_PINS `ifdef POWER_PINS
...@@ -120,12 +138,30 @@ SROM_Ax32 ...@@ -120,12 +138,30 @@ SROM_Ax32
.CLK (CLK), // input .CLK (CLK), // input
.TEST (TEST), // input .TEST (TEST), // input
.NRST (NRST), // active low reset .NRST (NRST), // active low reset
.P0 (P0), .P0 (P0[7:0]),
.P1 (P1), .P1 (P1[7:0]),
.SWDIO (SWDIOTMS), .SWDIO (SWDIOTMS),
.SWDCK (SWCLKTCK) .SWDCK (SWCLKTCK)
); );
`else
nanosoc_chip_pads
u_nanosoc_chip_pads (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
.VDDACC (VDDACC),
`endif
.CLK (CLK), // input
.TEST (TEST), // input
.NRST (NRST), // active low reset
.P0 (P0[15:0]),
.P1 (P1[15:0]),
.SWDIO (SWDIOTMS),
.SWDCK (SWCLKTCK)
);
`endif
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Source for clock and reset // Source for clock and reset
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
...@@ -658,22 +694,21 @@ nanosoc_ft1248x1_track ...@@ -658,22 +694,21 @@ nanosoc_ft1248x1_track
pulldown(debug_err); pulldown(debug_err);
//Tristate logic for GPIO connection //Tristate logic for GPIO connection
bufif1 (debug_command[5], P0[29-16], debug_test_en); bufif1 (P0[7], debug_running, debug_test_en);
bufif1 (debug_command[4], P0[28-16], debug_test_en); bufif1 (P0[6], debug_err, debug_test_en);
bufif1 (debug_command[3], P0[27-16], debug_test_en); bufif1 (debug_command[5], P0[3], debug_test_en);
bufif1 (debug_command[2], P0[26-16], debug_test_en); bufif1 (debug_command[4], P0[4], debug_test_en);
bufif1 (debug_command[1], P0[25-16], debug_test_en); bufif1 (debug_command[3], P0[3], debug_test_en);
bufif1 (debug_command[0], P0[24-16], debug_test_en); bufif1 (debug_command[2], P0[2], debug_test_en);
bufif1 (debug_command[1], P0[1], debug_test_en);
bufif1 (P0[31-16], debug_running, debug_test_en); bufif1 (debug_command[0], P0[0], debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
cmsdk_debug_tester #(.ROM_MEMFILE((BE==1) ? "debugtester_be.hex" : "debugtester_le.hex")) cmsdk_debug_tester #(.ROM_MEMFILE((BE==1) ? "debugtester_be.hex" : "debugtester_le.hex"))
u_cmsdk_debug_tester u_cmsdk_debug_tester
( (
// Clock and Reset // Clock and Reset
.CLK (CLK), .CLK (CLK),
.PORESETn (NRST), .PORESETn (NRST_ext),
// Command Interface // Command Interface
.DBGCMD (debug_command[5:0]), .DBGCMD (debug_command[5:0]),
......
verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
View file @ 234233bf
...@@ -114,12 +114,12 @@ localparam BUFSIZE = (64 * 1024); ...@@ -114,12 +114,12 @@ localparam BUFSIZE = (64 * 1024);
$write("** %m : input file length measured as: %d **\n", flen); $write("** %m : input file length measured as: %d **\n", flen);
if (flen > 0) flen=flen-1; // correct for extra char count(???) if (flen > 0) flen=flen-1; // correct for extra char count(???)
// now output the entire adp buffer to the stream // now output the entire adp buffer to the stream
flen = flen + clen+25+1; flen = flen + clen+25;
fp = 0; fp = 0;
valid <= 0; valid <= 0;
begin begin
@(posedge aresetn); @(posedge aresetn);
while (fp < flen) begin while (fp <= flen) begin
@(posedge aclk); @(posedge aclk);
data8 <= adpbuf[fp]; data8 <= adpbuf[fp];
fp = fp + 1; fp = fp + 1;
......