Add accelerator only Synthesis

ASIC/accelerator_only/Cadence/scripts/genus.tcl

+set_db init_lib_search_path $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/
+set BASE_LIB sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB"
+
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+elaborate accelerator_subsystem
+
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/accelerator_only/accel_constraints.sdc 
+
+set_db delete_unloaded_insts false
+set_db optimize_constant_1_flops false
+set_db optimize_constant_0_flops false
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_area_784.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_timing_784.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_gates_784.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/reports/syn_accel_power_784.rep
+
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/accel/netlist/accel.v
+

ASIC/accelerator_only/accel_constraints.sdc

+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis 
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### CLOCK DEFINITION
+
+set EXTCLK "clk";
+set_units -time ns;
+
+set_units -capacitance pF;
+set EXTCLK_PERIOD 4;
+
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports HCLK]
+
+set SKEW 0.200
+set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
+
+set MINRISE 0.20
+set MAXRISE 0.25
+set MINFALL 0.20
+set MAXFALL 0.25
+
+set_clock_transition -rise -min $MINRISE [get_clocks $EXTCLK]
+set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+
+#### DELAY DEFINITION
+
+set_max_capacitance 3 [all_outputs]
+set_max_fanout 10 [all_inputs]
\ No newline at end of file

ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v

@@ -74,15 +74,12 @@ module nanosoc_chip_pads (
   wire          swdclk_i;
   wire          VSSIO;
 
-  assign VSSIO = VSS;
  // --------------------------------------------------------------------------------
  // Cortex-M0 nanosoc Microcontroller
  // --------------------------------------------------------------------------------
 
   nanosoc_chip u_nanosoc_chip (
 `ifdef POWER_PINS
-  .VDDIO      (VDDIO),
-  .VSSIO      (VSSIO),
   .VDD        (VDD),
   .VSS        (VSS),
   .VDDACC     (VDDACC),

ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v

@@ -79,8 +79,6 @@ module nanosoc_chip_pads (
 
   nanosoc_chip u_nanosoc_chip (
 `ifdef POWER_PINS
-  .VDDIO      (VDDIO),
-  .VSSIO      (VSSIO),
   .VDD        (VDD),
   .VSS        (VSS),
   .VDDACC     (VDDACC),

ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v

@@ -80,8 +80,6 @@ module nanosoc_chip_pads (
 
   nanosoc_chip u_nanosoc_chip (
 `ifdef POWER_PINS
-  .VDDIO      (VDDIO),
-  .VSSIO      (VSSIO),
   .VDD        (VDD),
   .VSS        (VSS),
   .VDDACC     (VDDACC),