modify debug tests and testbench harness for 8-bit GPIO0 chips (44-pin for example) (234233bf) · Commits · SoCLabs / NanoSoC Tech · GitLab

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234233bf

Commit 234233bf authored 1 year ago by dwf1m12

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modify debug tests and testbench harness for 8-bit GPIO0 chips (44-pin for example)

parent 43092cb3

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software/common/debug_tests/debug_tests.h 13 additions, 23 deletions

software/common/debug_tests/debug_tests.h
testcodes/generic/mcu_debugtester_interface.h 13 additions, 24 deletions

testcodes/generic/mcu_debugtester_interface.h
verif/tb/verilog/nanosoc_tb.v 49 additions, 14 deletions

verif/tb/verilog/nanosoc_tb.v
verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v 2 additions, 2 deletions

verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v

with 77 additions and 63 deletions

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