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  • soclabs/nanosoc_tech
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software/common/validation/dma_tests.c
View file @ 778e3f5a
......@@ -297,7 +297,7 @@ void dma_memory_copy (unsigned int src, unsigned int dest, unsigned int size, un
(size << 21) | /* dst_prot_ctrl - HPROT[3:1] */
(size << 18) | /* src_prot_ctrl - HPROT[3:1] */
// (0 << 14) | /* R_power */
(4 << 14) | /* R_power for 16-word block transfer*/
(4 << 14) | /* R_power set for up to 16 transfers */
((num-1)<< 4) | /* n_minus_1 */
(0 << 3) | /* next_useburst */
(2 << 0) ; /* cycle_ctrl - auto */
......@@ -356,6 +356,21 @@ int dma_simple_test(void)
}
}
// then as 16 byte transfers
dma_memory_copy ((unsigned int) &source_data_array[0],(unsigned int) &dest_data_array[0], 0, 16);
do { /* Wait until PL230 DMA controller return to idle state */
current_state = (CMSDK_DMA->DMA_STATUS >> 4) & 0xF;
} while (current_state!=0);
for (i=0;i<4;i++) {
/* Debugging printf: */
/*printf (" - dest[i] = %x\n", dest_data_array[i]);*/
if (dest_data_array[i]!= i){
printf ("ERROR:dest_data_array[%d], expected %x, actual %x\n", i, i, dest_data_array[i]);
err_code |= (1<<i);
}
}
/* Generate return value */
if (err_code != 0) {
printf ("ERROR : simple DMA failed (0x%x)\n", err_code);
......
synthesis/ICC2/icc_shell.tcl
View file @ 778e3f5a
......@@ -23,10 +23,11 @@ read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r
read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
link_block
initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all}
initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -macro_utilization 0.2 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all}
create_io_ring -name main_io
explore_logic_hierarchy -organize
......@@ -49,9 +50,7 @@ set_app_options -list {clock_opt.place.effort {high}}
set_app_options -list {place_opt.flow.clock_aware_placement {true}}
set_app_options -list {place_opt.final_place.effort {high}}
set_app_options -list {clock_opt.hold.effort {ultra}}
set_app_options -list {opt.dft.optimize_scan_chain {false}}
set_app_options -list {opt.dft.do_repartition {false}}
set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/constraints.sdc
update_timing
......
synthesis/ICC2/place_memories.tcl
View file @ 778e3f5a
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.1} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.3} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.5} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.7} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner tl -anchor_corner tl -offset {0.15 -0.1} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner tl -anchor_corner tl -offset {0.55 -0.1} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.15 0.1} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.55 0.1} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom}] -target_orientation R270 -target_corner br -anchor_corner br -offset {-0.1 0.4} -offset_type scalable
create_macro_relative_location_placement
......
synthesis/ICC2/place_pins.tcl
View file @ 778e3f5a
set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1
set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3
set_individual_pin_constraints -ports {XTAL2 XTAL1 VDD VDDIO} -sides 2
set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIOTMS SWCLKTCK} -sides 4
set_individual_pin_constraints -ports {CLK TEST VDD VDDIO} -sides 2
set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4
place_pins -self
\ No newline at end of file
synthesis/constraints.sdc
View file @ 778e3f5a
......@@ -19,8 +19,8 @@ set_units -capacitance 1.0pF;
set EXTCLK_PERIOD 4;
set SWDCLK_PERIOD 20;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports XTAL1]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWCLKTCK]
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.200
set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
......@@ -44,10 +44,10 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
#### DELAY DEFINITION
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports TEST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIOTMS]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWCLKTCK]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIO]
set_max_capacitance 0.5 [all_outputs]
set_max_fanout 10 [all_inputs]
\ No newline at end of file
synthesis/genus.tcl
View file @ 778e3f5a
......@@ -8,6 +8,14 @@ source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
elaborate nanosoc_chip_pads
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/synthesis/constraints.sdc
set_db dft_scan_style muxed_scan
define_test_signal -function test_mode TEST
define_test_signal -function shift_enable SWDIO -shared_input
define_test_signal -function scan_clock SWDCK -shared_input
define_test_signal -function async_set_reset -active low NRST
check_dft_rules
set_db syn_generic_effort high
set_db syn_map_effort high
......@@ -22,6 +30,12 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_powe
write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
connect_scan_chains -auto_create_chains
report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_chains.rep
report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_setup.rep
report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_registers.rep
write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_dft_abstract_model
write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
exit
synthesis/io_plan.tcl
View file @ 778e3f5a
......@@ -5,9 +5,9 @@
###############################
### Pin Place
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {XTAL1 XTAL2 NRST VDD VDDIO}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {CLK TEST NRST VDD VDDIO}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIOTMS SWCLKTCK VSS VSSIO}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIO SWDCK VSS VSSIO}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 30 -pin {{P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]} {P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}}
......