Add scan chain support to genus and ICC

synthesis/ICC2/icc_shell.tcl

@@ -23,10 +23,11 @@ read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r
 
 
 read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
+read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
 link_block
 
 
-initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all}
+initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -macro_utilization 0.2 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all}
 create_io_ring -name main_io
 explore_logic_hierarchy -organize
 
@@ -49,9 +50,7 @@ set_app_options -list {clock_opt.place.effort {high}}
 set_app_options -list {place_opt.flow.clock_aware_placement {true}}
 set_app_options -list {place_opt.final_place.effort {high}}
 set_app_options -list {clock_opt.hold.effort {ultra}}
-set_app_options -list {opt.dft.optimize_scan_chain {false}}
-set_app_options -list {opt.dft.do_repartition {false}}
-set_app_options -list {place.coarse.continue_on_missing_scandef {true}}
+
 
 read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/constraints.sdc
 update_timing

synthesis/ICC2/place_memories.tcl

-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.1} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.3} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.5} -offset_type scalable
-set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.1 0.7} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner tl -anchor_corner tl -offset {0.15 -0.1} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner tl -anchor_corner tl -offset {0.55 -0.1} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.15 0.1} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf}] -target_orientation R90 -target_corner bl -anchor_corner bl -offset {0.55 0.1} -offset_type scalable
 set_macro_relative_location -target_object [get_cell {u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom}] -target_orientation R270 -target_corner br -anchor_corner br -offset {-0.1 0.4} -offset_type scalable
 create_macro_relative_location_placement
 

synthesis/genus.tcl

@@ -8,6 +8,14 @@ source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
 elaborate nanosoc_chip_pads
 read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/synthesis/constraints.sdc 
 
+set_db dft_scan_style muxed_scan
+define_test_signal -function test_mode TEST
+define_test_signal -function shift_enable SWDIO -shared_input
+define_test_signal -function scan_clock SWDCK -shared_input
+define_test_signal -function async_set_reset -active low NRST
+check_dft_rules
+
+
 set_db syn_generic_effort high
 set_db syn_map_effort high
 
@@ -22,6 +30,12 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_powe
 
 write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
 
+connect_scan_chains -auto_create_chains
+report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_chains.rep
+report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_setup.rep
+report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_registers.rep
 
+write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_dft_abstract_model
+write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
 
 exit