Update ASIC constraints with new pin names

synthesis/ICC2/place_pins.tcl

 set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1
 set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3
-set_individual_pin_constraints -ports {XTAL2 XTAL1 VDD VDDIO} -sides 2
-set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIOTMS SWCLKTCK} -sides 4
+set_individual_pin_constraints -ports {CLK TEST VDD VDDIO} -sides 2
+set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4
 
 place_pins -self
\ No newline at end of file

synthesis/constraints.sdc

@@ -19,8 +19,8 @@ set_units -capacitance 1.0pF;
 set EXTCLK_PERIOD 4;
 set SWDCLK_PERIOD 20;
 
-create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports XTAL1]
-create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWCLKTCK]
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
+create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
 
 set SKEW 0.200
 set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
@@ -44,10 +44,10 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
 #### DELAY DEFINITION
 
 set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports TEST]
 set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
 set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
-set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIOTMS]
-set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWCLKTCK]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIO]
 
 set_max_capacitance 0.5 [all_outputs]
 set_max_fanout 10 [all_inputs]
\ No newline at end of file

synthesis/io_plan.tcl

@@ -5,9 +5,9 @@
 ###############################
 
 ### Pin Place 
-edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {XTAL1 XTAL2 NRST VDD VDDIO}
+edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {CLK TEST NRST VDD VDDIO}
 
-edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIOTMS SWCLKTCK VSS VSSIO}
+edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIO SWDCK VSS VSSIO}
 
 edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 30 -pin {{P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]} {P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}}