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SoCLabs
NanoSoC Tech
Commits
1ebe89b6929421c7fe0d0247fb8c3e857c584b24
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10
main
default
protected
feat_dma230_dataio
feat_qspi_rom
feat_extio
feat_dmax4
feat_dma350
feat_nanosoc_regions
feat_accel_decouple
dev
feat_accel_hash_stream
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1
nanosoc-2023
11 results
nanosoc_tech
ASIC
44pin
Cadence
scripts
power_plan.tcl
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authors
dam1n19
dam1n19
dwf1m12
dwf1m12
dwn1c21
dwn1c21
eb3u21
eb3u21
hhp1n22
hhp1n22
John Darlington
JohnD
6 authors
Feb 01, 2024
update PnR include miniASIC m scheme and bondpad place
· 1ebe89b6
Daniel Newbrook
authored
1 year ago
1ebe89b6
Jan 22, 2024
Update PnR flow inc Tie offs
· 23ed834a
Daniel Newbrook
authored
1 year ago
23ed834a
Jan 12, 2024
Add DFT option to backend
· e386ca57
Daniel Newbrook
authored
1 year ago
e386ca57
Dec 05, 2023
Add 3rd channel to dma350
· 48919e69
Daniel Newbrook
authored
1 year ago
48919e69
Split ASIC flow for 28 44 and 60 pin
· 1db4da7e
Daniel Newbrook
authored
1 year ago
1db4da7e
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