Add DFT option to backend
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- ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf 1 addition, 1 deletionASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
- ASIC/44pin/Cadence/scripts/design_import.tcl 5 additions, 4 deletionsASIC/44pin/Cadence/scripts/design_import.tcl
- ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl 46 additions, 0 deletionsASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
- ASIC/44pin/Cadence/scripts/genus.tcl 43 additions, 32 deletionsASIC/44pin/Cadence/scripts/genus.tcl
- ASIC/44pin/Cadence/scripts/genus_nodft.tcl 69 additions, 0 deletionsASIC/44pin/Cadence/scripts/genus_nodft.tcl
- ASIC/44pin/Cadence/scripts/nanosoc.mmmc 5 additions, 4 deletionsASIC/44pin/Cadence/scripts/nanosoc.mmmc
- ASIC/44pin/Cadence/scripts/place_macros.tcl 15 additions, 15 deletionsASIC/44pin/Cadence/scripts/place_macros.tcl
- ASIC/44pin/Cadence/scripts/pnr_flow.tcl 26 additions, 8 deletionsASIC/44pin/Cadence/scripts/pnr_flow.tcl
- ASIC/44pin/Cadence/scripts/power_plan.tcl 4 additions, 4 deletionsASIC/44pin/Cadence/scripts/power_plan.tcl
- ASIC/constraints.sdc 10 additions, 7 deletionsASIC/constraints.sdc
- ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v 5 additions, 3 deletionsASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
- makefile 2 additions, 2 deletionsmakefile
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