From e386ca57ca80abe46079877dc3d12ee04da06987 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Fri, 12 Jan 2024 12:21:02 +0000
Subject: [PATCH] Add DFT option to backend
---
ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf | 2 +-
ASIC/44pin/Cadence/scripts/design_import.tcl | 9 ++-
.../Cadence/scripts/design_import_noDFT.tcl | 46 ++++++++++++
ASIC/44pin/Cadence/scripts/genus.tcl | 75 +++++++++++--------
ASIC/44pin/Cadence/scripts/genus_nodft.tcl | 69 +++++++++++++++++
ASIC/44pin/Cadence/scripts/nanosoc.mmmc | 9 ++-
ASIC/44pin/Cadence/scripts/place_macros.tcl | 30 ++++----
ASIC/44pin/Cadence/scripts/pnr_flow.tcl | 34 +++++++--
ASIC/44pin/Cadence/scripts/power_plan.tcl | 8 +-
ASIC/constraints.sdc | 17 +++--
.../tsmc65lp/nanosoc_chip_pads_44pin.v | 8 +-
makefile | 4 +-
12 files changed, 231 insertions(+), 80 deletions(-)
create mode 100644 ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
create mode 100644 ASIC/44pin/Cadence/scripts/genus_nodft.tcl
diff --git a/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf b/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
index e0869e5..7eb1881 100644
--- a/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
+++ b/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
@@ -2,7 +2,7 @@ set_cpf_version 1.1
set_design nanosoc_chip_pads
create_power_domain -name TOP -default
-create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08
diff --git a/ASIC/44pin/Cadence/scripts/design_import.tcl b/ASIC/44pin/Cadence/scripts/design_import.tcl
index 894dd92..9bfbe84 100644
--- a/ASIC/44pin/Cadence/scripts/design_import.tcl
+++ b/ASIC/44pin/Cadence/scripts/design_import.tcl
@@ -22,16 +22,17 @@ set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tp
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
+set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs
-read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${ROM_LEF}]
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
### Reading Netlist
read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
### Read DEF scan chain
-#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
+read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
### Initializing the Design
init_design
@@ -39,9 +40,9 @@ init_design
### Adjusting the GUI
gui_fit
-ungroup u_nanosoc_chip_u_system
+#ungroup u_nanosoc_chip_u_system
-create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 150.0 150.0 150.0 150.0
+create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 140.0 140.0 140.0 140.0
read_power_intent -cpf ../cpf/nanosoc_imp.cpf
diff --git a/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl b/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
new file mode 100644
index 0000000..2aaa9d6
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
@@ -0,0 +1,46 @@
+#########################################
+# File : Design Import Logic
+# Date : 22nd May 2022
+# Author : Srimanth Tenneti
+# Description : MMMC + Design Import
+#########################################
+
+### Settting PG Nets
+set_db init_power_nets {VDD VDDIO VDDACC}
+set_db init_ground_nets {VSS VSSIO}
+
+### Processing MMMC
+read_mmmc nanosoc.mmmc
+
+# Set library paths
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
+set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${RF_08K_LEF} ${ROM_LEF}]
+
+### Reading Netlist
+read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v
+
+### Initializing the Design
+init_design
+
+### Adjusting the GUI
+gui_fit
+
+#ungroup u_nanosoc_chip_u_system
+
+create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 140.0 140.0 140.0 140.0
+
+read_power_intent -cpf ../cpf/nanosoc_imp.cpf
+
+
diff --git a/ASIC/44pin/Cadence/scripts/genus.tcl b/ASIC/44pin/Cadence/scripts/genus.tcl
index 93d43c7..35cf920 100644
--- a/ASIC/44pin/Cadence/scripts/genus.tcl
+++ b/ASIC/44pin/Cadence/scripts/genus.tcl
@@ -13,52 +13,66 @@
#-----------------------------------------------------------------------------
## -- Setup libraries -- ##
-set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
+set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
+set RF_08K rf_08k_ss_1p08v_1p08v_125c.lib
set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
create_library_domain domain1
-set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER"
+set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $RF_08K $ROM_LIB $IO_PAD_DRIVER"
+# set_dont_touch SDFF*
+check_library > syn_lib_check.log
## -- Load power intent for top and accelerator power domains -- ##
read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
## -- Uncomment if you want to preserve hierarchy -- ##
#set_db auto_ungroup none
-
+
## -- Read in RTL and elaborate top level
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
elaborate nanosoc_chip_pads
+# Preserve hierarchy for M0.
+# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
+
## -- Apply power intent and check library and CPF -- ##
apply_power_intent
-check_library > syn_lib_check.log
-check_cpf > syn_cpf_check.log
+check_cpf -license lpgxl > syn_cpf_check.log
commit_power_intent
check_power_structure -license lpgxl > syn_pow_check.log
## -- Read constraints -- ##
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
-#set_db dft_scan_style muxed_scan
-#set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 1
-
-#read_dft_abstract_model nanosoc_dft_abstract_model
-#define_test_signal -name TEST -active high -function test_mode -index 0 TEST
-#define_test_signal -name SWDCK -active high -function scan_clock -index 0 SWDCK
-#define_test_signal -name NRST -active low -function async_set_reset -index 0 NRST
-#define_test_signal -name SWDIO -active high -function shift_enable -default -index 0 SWDIO
-#define_test_signal -name CLK -active high -function test_clock -index 0 CLK
-
-#define_scan_chain -name chain_ACCEL -sdi DFT_SDI_1 -sdo DFT_SDO_1 -shared_output
-#define_scan_chain -name chain_TOP -sdi DFT_SDI_2 -sdo DFT_SDO_2 -shared_output
-
-
-#check_dft_rules
-#fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin SWDCK
+set_db dft_scan_style muxed_scan
+set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 4
+set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
+define_test_signal -name TEST -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
+define_test_signal -name CLK -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
+define_test_signal -name NRST -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
+define_test_signal -name SWDCK -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SWDCK
+define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
+define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
+define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
+define_scan_chain -name chain_TOP_3 -sdi P0[3] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[3] -sdo P1[3] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[3] -shared_output -shared_input
+
+fix_pad_cfg -mode input -test_control TEST P0[0]
+fix_pad_cfg -mode input -test_control TEST P0[1]
+fix_pad_cfg -mode input -test_control TEST P0[2]
+fix_pad_cfg -mode input -test_control TEST P0[3]
+
+fix_pad_cfg -mode output -test_control TEST P1[0]
+fix_pad_cfg -mode output -test_control TEST P1[1]
+fix_pad_cfg -mode output -test_control TEST P1[2]
+fix_pad_cfg -mode output -test_control TEST P1[3]
+
+check_dft_rules
+fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin CLK
+fix_dft_violations -test_control TEST -async_set
set_db syn_generic_effort high
set_db syn_map_effort high
@@ -66,10 +80,8 @@ set_db syn_map_effort high
syn_generic
syn_map
-#convert_to_scan
-
-#connect_scan_chains -chains chain_ACCEL -power_domain ACCEL -incremental
-#connect_scan_chains -chains chain_TOP -power_domain TOP -incremental
+convert_to_scan
+connect_scan_chains
syn_opt
@@ -84,12 +96,11 @@ write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chi
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
-#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
-#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
-#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
-#write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_44pin
-
-#write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_44pin
-#write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
+report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
+report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
+report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
+write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_44pin
+write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_44pin
+write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
diff --git a/ASIC/44pin/Cadence/scripts/genus_nodft.tcl b/ASIC/44pin/Cadence/scripts/genus_nodft.tcl
new file mode 100644
index 0000000..a9bbe21
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/genus_nodft.tcl
@@ -0,0 +1,69 @@
+#-----------------------------------------------------------------------------
+# NanoSoC gate synthesis script for Cadence Genus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# run: genus -f genus.tcl
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Srimanth Tenneti
+#
+# Copyright (C) 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+## -- Setup libraries -- ##
+set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
+set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
+set RF_08K rf_08k_ss_1p08v_1p08v_125c.lib
+set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
+set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $RF_08K $ROM_LIB $IO_PAD_DRIVER"
+# set_dont_touch SDFF*
+check_library > syn_lib_check.log
+
+## -- Load power intent for top and accelerator power domains -- ##
+read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
+
+## -- Uncomment if you want to preserve hierarchy -- ##
+#set_db auto_ungroup none
+
+## -- Read in RTL and elaborate top level
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
+elaborate nanosoc_chip_pads
+
+# Preserve hierarchy for M0.
+# set_db hinst:nanosoc_chip_pads/u_nanosoc_chip/u_system/u_ss_cpu/u_cpu_0/u_slcorem0_integration/u_cortexm0 .ungroup_ok false
+
+## -- Apply power intent and check library and CPF -- ##
+apply_power_intent
+check_cpf -license lpgxl > syn_cpf_check.log
+commit_power_intent
+check_power_structure -license lpgxl > syn_pow_check.log
+
+## -- Read constraints -- ##
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
+
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_area_44pin.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_timing_44pin.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_gates_44pin.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_noDFT_nanosoc_power_44pin.rep
+
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v
+write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.vp
+
+write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.sdf
+
+write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_noDFT/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
diff --git a/ASIC/44pin/Cadence/scripts/nanosoc.mmmc b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
index b8c9c0d..3dd1598 100644
--- a/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
+++ b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
@@ -2,19 +2,20 @@ set phys_lib /research/AAA/phys_ip_library
set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
-set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_16k/
-set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/
+set ram_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_16k/
+set ram_08k_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_08k/
+set rom_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/bootrom/
set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
create_library_set -name default_libset_max\
-timing\
- [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${ram_08k_path}/rf_08k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
create_library_set -name default_libset_min\
-timing\
- [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${ram_08k_path}/rf_08k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
diff --git a/ASIC/44pin/Cadence/scripts/place_macros.tcl b/ASIC/44pin/Cadence/scripts/place_macros.tcl
index c24cda6..54a9f80 100644
--- a/ASIC/44pin/Cadence/scripts/place_macros.tcl
+++ b/ASIC/44pin/Cadence/scripts/place_macros.tcl
@@ -11,21 +11,21 @@
# relative floorplan
gui_set_draw_view fplan
delete_relative_floorplan -all
-create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
-create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
-move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
-update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6}
-add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
-create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
+move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
+update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420}
+add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
+create_partition -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 0 -min_pitch_right 0 -min_pitch_top 2 -min_pitch_bottom 0 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 0 0 0 -route_halo 0.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
-create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
-create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
-create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
-create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
-create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
-add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
\ No newline at end of file
+add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
diff --git a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
index 35ff13f..b97b31b 100644
--- a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
+++ b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
@@ -1,9 +1,21 @@
-######################################
-# Script : Place and Route Flow
-# Date : 25th May 2023
-# Author : Srimanth Tenneti
-# Description : Innovus PnR Flow
-######################################
+#-----------------------------------------------------------------------------
+# NanoSoC Place and route script for Cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# run: innovus -stylus -f pnr_flow.tcl
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Srimanth Tenneti
+#
+# Copyright (C) 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
+set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
+set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
+
puts "Starting PnR Flow ..."
@@ -26,16 +38,18 @@ source power_plan.tcl
source power_route.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
+uniquify nanosoc_chip_pads -verbose
### Placement
source place.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
+reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware false
-uniquify nanosoc_chip_pads -verbose
### CTS
source clock_tree_synthesis.tcl
+reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware true
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
@@ -71,6 +85,10 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_
gui_show
-
+write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
+ -map_file $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/tech.map \
+ -lib_name DesignLib \
+ -merge [list ${SC_GDS2} ${RF_16K_GDS2} ${ROM_VIA_GDS2}]\
+ -output_macros -unit 2000 -mode all
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
index 8e16398..0d81bb3 100644
--- a/ASIC/44pin/Cadence/scripts/power_plan.tcl
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -10,7 +10,7 @@ connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
-connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -override
+connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -override
### Top and Bottom Metal Declartions
set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
@@ -38,12 +38,12 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
-add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 50 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 58 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
# Connect Accelerator region
-select_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+select_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator
set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
@@ -69,7 +69,7 @@ add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing
deselect_obj -all
# connect Macros
-select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+select_obj [ list u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
set_db add_stripes_ignore_block_check false
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
diff --git a/ASIC/constraints.sdc b/ASIC/constraints.sdc
index 36ed5ab..1784a44 100644
--- a/ASIC/constraints.sdc
+++ b/ASIC/constraints.sdc
@@ -16,15 +16,15 @@ set SWDCLK "swdclk";
set_units -time ns;
set_units -capacitance pF;
-set EXTCLK_PERIOD 4;
-set SWDCLK_PERIOD 20;
+set EXTCLK_PERIOD 4.1666;
+set SWDCLK_PERIOD 16.66666;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.800
-set_clock_uncertainty [expr 0.15*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
-set_clock_uncertainty [expr 0.15*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
+set_clock_uncertainty [expr 0.17*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
+set_clock_uncertainty [expr 0.17*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
set MINRISE 0.20
set MAXRISE 0.25
@@ -43,9 +43,12 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
### Multicycle path through pads
-set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
-set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
-set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
+#set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
+set_false_path -through uPAD_SWDIO_IO
+set_false_path -through uPAD_P0_*
+set_false_path -through uPAD_P1_*
+#set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
+#set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
#### DELAY DEFINITION
diff --git a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
index c9acf2d..91e851e 100644
--- a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
+++ b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
@@ -35,6 +35,8 @@
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
+`include "gen_defines.v"
+
module nanosoc_chip_pads (
inout wire VDDIO,
inout wire VSSIO,
@@ -189,9 +191,9 @@ nanosoc_chip_cfg #(
.bist_enable (soc_bist_enable ),
.bist_in (soc_bist_in ), // soc bist control inputs
.bist_out (soc_bist_out ), // soc test status outputs
- .alt_mode (soc_alt_mode )// ALT MODE = UART
- .uart_rxd_i (soc_uart_rxd_i ) // UART RXD
- .uart_txd_o (soc_uart_txd_o ) // UART TXD
+ .alt_mode (soc_alt_mode ),// ALT MODE = UART
+ .uart_rxd_i (soc_uart_rxd_i ), // UART RXD
+ .uart_txd_o (soc_uart_txd_o ), // UART TXD
.swd_mode (soc_swd_mode ), // SWD mode
`endif
.clk_i(pad_clk_i),
diff --git a/makefile b/makefile
index 24d2647..bed9fc9 100644
--- a/makefile
+++ b/makefile
@@ -77,14 +77,14 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
- NANOSOC_DEFINES += DMAC_DMA350 POWER_PINS
+ NANOSOC_DEFINES += DMAC_0_PL230 DMAC_1_PL230 ASIC_TEST_PORTS POWER_PINS
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
TB_TOP ?= nanosoc_tb
- NANOSOC_DEFINES += DMAC_0_PL230
+ NANOSOC_DEFINES += DMAC_0_PL230 DMAC_1_PL230
endif
endif
--
GitLab