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Commit f0dbd8b3 authored by dwf1m12's avatar dwf1m12
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update paths to Cortex-M0 for AT510-BU-50000-r0p0-03rel2 bundle, and fix FPGA builds

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Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+ 1
− 0
View file @ f0dbd8b3
...@@ -82,6 +82,7 @@ read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v ...@@ -82,6 +82,7 @@ read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
read_verilog $soc_vlog/nanosoc_cpu.v read_verilog $soc_vlog/nanosoc_cpu.v
read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v
read_verilog $soc_vlog/nanosoc_sysio.v read_verilog $soc_vlog/nanosoc_sysio.v
read_verilog $soc_vlog/soclabs_ahb_aes128_ctrl.v
read_verilog $soc_vlog/nanosoc_chip.v read_verilog $soc_vlog/nanosoc_chip.v
read_verilog $soc_vlog/nanosoc_chip_pads.v read_verilog $soc_vlog/nanosoc_chip_pads.v
......
Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+ 38
− 32
View file @ f0dbd8b3
...@@ -821,44 +821,50 @@ localparam CORTEX_M0 = 1; ...@@ -821,44 +821,50 @@ localparam CORTEX_M0 = 1;
// ************************************************ // ************************************************
// ************************************************ // ************************************************
// //
// ADD YOUR EXPERIMENTAL AHB-MAPPED I/O HERE // ADD YOUR EXPERIMENTAL AHB-MAPPED WRAPPER HERE
// //
// //
// ************************************************ // ************************************************
soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSEL_exp),
.ahb_haddr16 (HADDR_exp[15:0]),
.ahb_htrans (HTRANS_exp),
.ahb_hwrite (HWRITE_exp),
.ahb_hsize (HSIZE_exp),
// .ahb_hburst (HBURST_exp),
.ahb_hprot (HPROT_exp),
.ahb_hwdata (HWDATA_exp),
// .ahb_hmastlock (HMASTLOCK_exp),
.ahb_hready (HREADYMUX_exp),
.ahb_hrdata (HRDATA_exp),
.ahb_hreadyout (HREADYOUT_exp),
.ahb_hresp (HRESP_exp),
.drq_ipdma128 ( ),
.dlast_ipdma128 (1'b0),
.drq_opdma128 ( ),
.dlast_opdma128 (1'b0),
.irq_key128 ( ),
.irq_ip128 ( ),
.irq_op128 ( ),
.irq_error ( ),
.irq_merged ( )
);
// // // Default slave
// dummy interface of the form: // cmsdk_ahb_default_slave u_ahb_exp (
// experimental_ip u_exp (
// .HCLK (HCLK), // .HCLK (HCLK),
// .HRESETn (HRESETn), // .HRESETn (HRESETn),
// .HSEL (HSEL_exp), // .HSEL (HSEL_exp),
// .HADDR (HADDR_exp),
// .HTRANS (HTRANS_exp), // .HTRANS (HTRANS_exp),
// .HWRITE (HWRITE_exp),
// .HSIZE (HSIZE_exp),
// .HBURST (HBURST_exp),
// .HPROT (HPROT_exp),
// .HWDATA (HWDATA_exp),
// .HMASTLOCK (HMASTLOCK_exp),
// .HREADY (HREADYMUX_exp), // .HREADY (HREADYMUX_exp),
// .HRDATA (HRDATA_exp),
// .HREADYOUT (HREADYOUT_exp), // .HREADYOUT (HREADYOUT_exp),
// .HRESP (HRESP_exp) // .HRESP (HRESP_exp)
// ); // );
// assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
// Default slave
cmsdk_ahb_default_slave u_ahb_exp (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL_exp),
.HTRANS (HTRANS_exp),
.HREADY (HREADYMUX_exp),
.HREADYOUT (HREADYOUT_exp),
.HRESP (HRESP_exp)
);
assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
assign HRUSER_exp = 2'b00; assign HRUSER_exp = 2'b00;
// ************************************************ // ************************************************
......
Cortex-M0/nanosoc/systems/mcu/verilog/soclabs_ahb_aes128_ctrl.v
+ 7
− 7
View file @ f0dbd8b3
...@@ -606,7 +606,7 @@ endmodule ...@@ -606,7 +606,7 @@ endmodule
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_core( module aes_core(
input wire clk, input wire clk,
...@@ -950,7 +950,7 @@ endmodule // aes_core ...@@ -950,7 +950,7 @@ endmodule // aes_core
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_encipher_block( module aes_encipher_block(
input wire clk, input wire clk,
...@@ -1438,7 +1438,7 @@ endmodule // aes_encipher_block ...@@ -1438,7 +1438,7 @@ endmodule // aes_encipher_block
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_decipher_block( module aes_decipher_block(
input wire clk, input wire clk,
...@@ -1963,7 +1963,7 @@ endmodule // aes_decipher_block ...@@ -1963,7 +1963,7 @@ endmodule // aes_decipher_block
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_key_mem( module aes_key_mem(
input wire clk, input wire clk,
...@@ -2399,7 +2399,7 @@ endmodule // aes_key_mem ...@@ -2399,7 +2399,7 @@ endmodule // aes_key_mem
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_sbox( module aes_sbox(
input wire [31 : 0] sboxw, input wire [31 : 0] sboxw,
...@@ -2725,7 +2725,7 @@ endmodule // aes_sbox ...@@ -2725,7 +2725,7 @@ endmodule // aes_sbox
// //
//====================================================================== //======================================================================
`default_nettype none ///`default_nettype none
module aes_inv_sbox( module aes_inv_sbox(
input wire [31 : 0] sboxw, input wire [31 : 0] sboxw,
......
Cortex-M0/nanosoc/systems/mcu/verilog/tbench_M0.vc
+ 12
− 12
View file @ f0dbd8b3
...@@ -106,22 +106,22 @@ ...@@ -106,22 +106,22 @@
// ============= Cortex-M0 Module search path ============= // ============= Cortex-M0 Module search path =============
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
// ============= Cortex-M0 Include file search path ============= // ============= Cortex-M0 Include file search path =============
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_dap/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
......
Cortex-M0/nanosoc/systems/mcu/verilog/v2html_M0.vc
+ 8
− 8
View file @ f0dbd8b3
...@@ -106,16 +106,16 @@ ...@@ -106,16 +106,16 @@
// ============= Cortex-M0 Module search path ============= // ============= Cortex-M0 Module search path =============
// guts of core not exposed, periphery only // guts of core not exposed, periphery only
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog -y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
// ============= Cortex-M0 Include file search path ============= // ============= Cortex-M0 Include file search path =============
// guts of core not exposed, periphery only // guts of core not exposed, periphery only
+incdi+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/cells
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/models/wrappers
+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog +incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/ualdis/verilog
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