Update .gitlab-ci.yml file

.gitlab-ci.yml

@@ -26,7 +26,7 @@ build-job:       # This job runs in the build stage, which runs first.
   script:
     - source /tools/Xilinx/Vivado/2021.2/.settings64-Vivado.sh
     - cd ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/
-    - source ./build_fpga_pynq_z2.scr
+#    - source ./build_fpga_pynq_z2.scr
 #    - FILE = ./ ./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit 
 #    - if test -f "$FILE"; then
 #    -   echo "Build successful"
@@ -37,6 +37,8 @@ build-job:       # This job runs in the build stage, which runs first.
     - ls ../../../../../../arm-AAA-ip/Cortex-M0/
     - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/
     - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
+    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/
+    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog/
   tags:
     - FPGA